linux.git/arch/arm/kernel/Makefile, branch v2.6.25

[ARM] 4736/1: Export atags to userspace and allow kexec to use customised atags

2008-02-04T13:21:03+00:00

Currently, the atags used by kexec are fixed to the ones originally used
to boot the kernel. This is less than ideal as changing the commandline,
initrd and other options would be a useful feature.

This patch exports the atags used for the current kernel to userspace
through an "atags" file in procfs. The presence of the file is
controlled by its own Kconfig option and cleans up several ifdef blocks
into a separate file. The tags for the new kernel are assumed to be at
a fixed location before the kernel image itself. The location of the
tags used to boot the original kernel is unimportant and no longer
saved.

Based on a patch from Uli Luckas 

Signed-off-by: Richard Purdie 
Acked-by: Uli Luckas 
Signed-off-by: Russell King

ARM kprobes: core code

2008-01-26T15:25:16+00:00

This is a full implementation of Kprobes including Jprobes and
Kretprobes support.

This ARM implementation does not follow the usual kprobes double-
exception model. The traditional model is where the initial kprobes
breakpoint calls kprobe_handler(), which returns from exception to
execute the instruction in its original context, then immediately
re-enters after a second breakpoint (or single-stepping exception)
into post_kprobe_handler(), each time the probe is hit..  The ARM
implementation only executes one kprobes exception per hit, so no
post_kprobe_handler() phase. All side-effects from the kprobe'd
instruction are resolved before returning from the initial exception.
As a result, all instructions are _always_ effectively boosted
regardless of the type of instruction, and even regardless of whether
or not there is a post-handler for the probe.

Signed-off-by: Abhishek Sagar 
Signed-off-by: Quentin Barnes 
Signed-off-by: Nicolas Pitre

ARM kprobes: instruction single-stepping support

2008-01-26T15:25:16+00:00

This is the code implementing instruction single-stepping for kprobes
on ARM.

To get around the limitation of no Next-PC and no hardware single-
stepping, all kprobe'd instructions are split into three camps:
simulation, emulation, and rejected. "Simulated" instructions are
those instructions which behavior is reproduced by straight C code.
"Emulated" instructions are ones that are copied, slightly altered
and executed directly in the instruction slot to reproduce their
behavior.  "Rejected" instructions are ones that could be simulated,
but work hasn't been put into simulating them. These instructions
should be very rare, if not unencountered, in the kernel. If ever
needed, code could be added to simulate them.

One might wonder why this and the ptrace singlestep facility are not
sharing some code.  Both approaches are fundamentally different because
the ptrace code regains control after the stepped instruction by installing
a breakpoint after the instruction itself, and possibly at the location
where the instruction might be branching to, instead of simulating or
emulating the target instruction.

The ptrace approach isn't suitable for kprobes because the breakpoints
would have to be moved back, and the icache flushed, everytime the
probe is hit to let normal code execution resume, which would have a
significant performance impact. It is also racy on SMP since another
CPU could, with the right timing, sail through the probe point without
being caught.  Because ptrace single-stepping always result in a
different process to be scheduled, the concern for performance is much
less significant.

On the other hand, the kprobes approach isn't (currently) suitable for
ptrace because it has no provision for proper user space memory
protection and translation, and even if that was implemented, the gain
wouldn't be worth the added complexity in the ptrace path compared to
the current approach.

So, until kprobes does support user space, both kprobes and ptrace are
best kept independent and separate.

Signed-off-by: Quentin Barnes 
Signed-off-by: Abhishek Sagar 
Signed-off-by: Nicolas Pitre

[ARM] Add stacktrace support and make oprofile use it

2007-04-28T08:59:37+00:00

Add support for stacktrace.  Use the new stacktrace code with
oprofile instead of it's version; there's no point having
multiple versions of stacktracing in the kernel.

Signed-off-by: Russell King

Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm

2007-02-19T21:18:39+00:00

* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (117 commits)
  [ARM] 4058/2: iop32x: set ->broken_parity_status on n2100 onboard r8169 ports
  [ARM] 4140/1: AACI stability add ac97 timeout and retries
  [ARM] 4139/1: AACI record support
  [ARM] 4138/1: AACI: multiple channel support for IRQ handling
  [ARM] 4211/1: Provide a defconfig for ns9xxx
  [ARM] 4210/1: base for new machine type "NetSilicon NS9360"
  [ARM] 4222/1: S3C2443: Remove reference to missing S3C2443_PM
  [ARM] 4221/1: S3C2443: DMA support
  [ARM] 4220/1: S3C24XX: DMA system initialised from sysdev
  [ARM] 4219/1: S3C2443: DMA source definitions
  [ARM] 4218/1: S3C2412: fix CONFIG_CPU_S3C2412_ONLY wrt to S3C2443
  [ARM] 4217/1: S3C24XX: remove the dma channel show at startup
  [ARM] 4090/2: avoid clash between PXA and SA1111 defines
  [ARM] 4216/1: add .gitignore entries for ARM specific files
  [ARM] 4214/2: S3C2410: Add Armzone QT2410
  [ARM] 4215/1: s3c2410 usb device:  per-platform vbus_draw
  [ARM] 4213/1: S3C2410 - Update definition of ADCTSC_XY_PST
  [ARM] 4098/1: ARM: rtc_lock only used with rtc_cmos
  [ARM] 4137/1: Add kexec support
  [ARM] 4201/1: SMP barriers pair needed for the secondary boot process
  ...

Fix up conflict due to typedef removal in sound/arm/aaci.h

[ARM] 4137/1: Add kexec support

2007-02-16T14:37:06+00:00

Add kexec support to ARM.

Improvements like commandline handling could be made but this patch gives
basic functional support. It uses the next available syscall number, 347.

Once the syscall number is known, userspace support will be
finalised/submitted to kexec-tools, various patches already exist.

Originally based on a patch by Maxim Syrchin but updated and forward
ported by various people.

Signed-off-by: Richard Purdie 
Signed-off-by: Russell King

[APM] ARM: Convert to use shared APM emulation.

2007-02-09T17:08:58+00:00

Signed-off-by: Ralf Baechle

[ARM] 3881/4: xscale: clean up cp0/cp1 handling

2006-12-03T17:52:22+00:00

XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek 
Acked-by: Dan Williams 
Signed-off-by: Russell King

[ARM] Add Integrator support for glibc outb() and friends

2006-08-28T11:47:05+00:00

Add the necessary call to register_isa_ports() so that glibc knows
where these are found on Integrator platforms.

Signed-off-by: Russell King

[ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure

2006-07-01T18:56:48+00:00

Patch from Lennert Buytenhek

This patch makes the iWMMXt context switch hook use the generic
thread notifier infrastructure that was recently merged in commit
d6551e884cf66de072b81f8b6d23259462c40baf.

Signed-off-by: Lennert Buytenhek 
Signed-off-by: Russell King