linux.git/arch/arm/include/asm/outercache.h, branch v3.17 Linux kernel source tree ARM: l2c: remove old .set_debug method 2014-05-29T23:50:35+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-16T19:38:25+00:00 678ea28b7c3cc9a7196192dc77dfc13513db3d5f We no longer need or require the .set_debug method; we handle everything it used to do via the .write_sec method instead. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
We no longer need or require the .set_debug method; we handle everything
it used to do via the .write_sec method instead.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: provide generic hook to intercept writes to secure registers 2014-05-29T23:48:39+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-16T17:38:08+00:00 8abd259f657d5742f96ffd46ed65feb11c44b1fb When Linux is running in the non-secure world, any write to a secure L2C register will generate an abort. Platforms normally have to call firmware to work around this. Provide a hook for them to intercept any L2C secure register write. l2c_write_sec() avoids writes to secure registers which are already set to the appropriate value, thus avoiding the overhead of needlessly calling into the secure monitor. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
When Linux is running in the non-secure world, any write to a secure
L2C register will generate an abort.  Platforms normally have to call
firmware to work around this.  Provide a hook for them to intercept
any L2C secure register write.

l2c_write_sec() avoids writes to secure registers which are already set
to the appropriate value, thus avoiding the overhead of needlessly
calling into the secure monitor.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: outer cache: add WARN_ON() to outer_disable() 2014-05-29T23:47:23+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-16T13:14:38+00:00 1f1d5b745a4617a2cb2ffd8f4a9bc3be664cfc98 Add WARN_ON() conditions to outer_disable() to ensure that its requirements aren't violated. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Add WARN_ON() conditions to outer_disable() to ensure that its
requirements aren't violated.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: outer cache: add documentation of outer cache functions 2014-05-22T15:38:46+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-16T10:52:55+00:00 bc4f94d85cad6035d02d2bed1b27f9bea7e7b6e6 Add some documentation to cover the outer cache functions so that their requirements can be better understood. Of particular note are the flush_all() and disable() methods which must not be called except in very specific circumstances. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Add some documentation to cover the outer cache functions so that their
requirements can be better understood.  Of particular note are the
flush_all() and disable() methods which must not be called except in
very specific circumstances.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: l2c: remove outer_inv_all() method 2014-05-22T15:21:35+00:00 Russell King rmk+kernel@arm.linux.org.uk 2014-03-15T16:47:44+00:00 265c271c822bd57677e3b286389487fd45e6960d No one ever calls this function anywhere in the kernel, so let's completely remove it from the outer cache API and turn it into an internal-only thing. Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
No one ever calls this function anywhere in the kernel, so let's
completely remove it from the outer cache API and turn it into an
internal-only thing.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: move outer_cache declaration out of ifdef 2013-08-23T01:48:41+00:00 Rob Herring rob.herring@calxeda.com 2013-08-18T01:12:57+00:00 0b53c11d533a8f6688d73fad0baf67dd08ec1b90 Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that outer_cache can be used inside IS_ENABLED condition. Signed-off-by: Rob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> 
Move the outer_cache declaration of the CONFIG_OUTER_CACHE ifdef so that
outer_cache can be used inside IS_ENABLED condition.

Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
ARM: 7639/1: cache-l2x0: add missed dummy outer_resume entry 2013-02-06T09:33:07+00:00 Barry Song Baohua.Song@csr.com 2013-02-04T06:46:57+00:00 4e79a62d84b9a3b84c609d73382415c71d911a4c Commit 91c2ebb90b1890a (ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode) added resume entry for l2 in secure mode, but it missed the dummy entry when CONFIG_CACHE_L2X0 is not set. (Commit text edited by rmk.) Signed-off-by: Barry Song <Baohua.Song@csr.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
Commit 91c2ebb90b1890a (ARM: 7114/1: cache-l2x0: add resume entry for l2
in secure mode) added resume entry for l2 in secure mode, but it missed
the dummy entry when CONFIG_CACHE_L2X0 is not set.

(Commit text edited by rmk.)

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ARM: 7114/1: cache-l2x0: add resume entry for l2 in secure mode 2011-10-17T08:11:51+00:00 Barry Song Baohua.Song@csr.com 2011-09-30T13:43:12+00:00 91c2ebb90b1890abc648ba9dec5608cbc97e1cb9 we save the l2x0 registers at the first initialization, and platform codes can get them to restore l2x0 status after wakeup. Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Barry Song <Baohua.Song@csr.com> Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Tested-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk> 
we save the l2x0 registers at the first initialization, and platform codes
can get them to restore l2x0 status after wakeup.

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Reviewed-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Merge branches 'fixes', 'pgt-next' and 'versatile' into devel 2011-03-20T09:32:12+00:00 Russell King rmk+kernel@arm.linux.org.uk 2011-03-20T09:32:12+00:00 196f020fbbb83d246960548e73a40fd08f3e7866 






ARM: 6795/1: l2x0: Errata fix for flush by Way operation can cause data corrupti
2011-03-09T00:18:34+00:00

Santosh Shilimkar
santosh.shilimkar@ti.com

2011-03-08T05:59:54+00:00

2839e06c95d12ada034cf9b63da60334c7c6358b

PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

This patch also removes any OMAP dependency on PL310 Errata's

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>





PL310 implements the Clean & Invalidate by Way L2 cache maintenance
operation (offset 0x7FC). This operation runs in background so that
PL310 can handle normal accesses while it is in progress. Under very
rare circumstances, due to this erratum, write data can be lost when
PL310 treats a cacheable write transaction during a Clean & Invalidate
by Way operation.

Workaround:
Disable Write-Back and Cache Linefill (Debug Control Register)
Clean & Invalidate by Way (0x7FC)
Re-enable Write-Back and Cache Linefill (Debug Control Register)

This patch also removes any OMAP dependency on PL310 Errata's

Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>