linux.git/Documentation/gpu/amdgpu, branch v7.2-rc1 Linux kernel source tree Documentation/amdgpu: Add documentation for Peak Tops Limiter (PTL) sysfs interface 2026-05-11T19:55:55+00:00 Perry Yuan perry.yuan@amd.com 2026-02-08T16:42:05+00:00 aa86e750d0ff79c179772b9d3a95375c02a7d191 The PTL (Peak Tops Limiter) feature exposes per-GPU sysfs files under /sys/class/drm/cardX/device/ptl/ to allow users to enable or disable PTL, configure preferred data formats, and query supported formats. The usage of these sysfs files is not always obvious, so add documentation to describe their purpose and provide concrete usage examples. V3 changes: * format show will display preferred formats instead of N/A (Alex) Signed-off-by: Perry Yuan <perry.yuan@amd.com> Suggested-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
The PTL (Peak Tops Limiter) feature exposes per-GPU sysfs files under
/sys/class/drm/cardX/device/ptl/ to allow users to enable or disable PTL,
configure preferred data formats, and query supported formats. The usage
of these sysfs files is not always obvious, so add documentation to
describe their purpose and provide concrete usage examples.

V3 changes:
 * format show will display preferred formats instead of N/A (Alex)

Signed-off-by: Perry Yuan <perry.yuan@amd.com>
Suggested-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Add TCC, update TCP in amdgpu glossary 2026-04-24T14:50:06+00:00 Timur Kristóf timur.kristof@gmail.com 2026-04-18T21:49:32+00:00 85f284b5aece41d3d8242e3c266774d543a2f8be These are the L2 and L1 cache on some AMD GPU architectures. Add them to the glossary, keeping existing alphabetical order. Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
These are the L2 and L1 cache on some AMD GPU architectures.
Add them to the glossary, keeping existing alphabetical order.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd: Update IP versions for Gorgon Point products 2026-01-20T22:19:01+00:00 Mario Limonciello mario.limonciello@amd.com 2026-01-15T21:45:43+00:00 e53278b220df98fd5261cbeeef75519d00930029 Gorgon point products were announced. Add the IP versions for each product. Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-hx-pro-475.html Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-hx-pro-470.html Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-pro-465.html Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-7-pro-450.html Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-5-pro-440.html Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-5-pro-435.html Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Gorgon point products were announced. Add the IP versions for each
product.

Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-hx-pro-475.html
Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-hx-pro-470.html
Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-9-pro-465.html
Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-7-pro-450.html
Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-5-pro-440.html
Link: https://www.amd.com/en/products/processors/laptop/ryzen-pro/ai-400-series/amd-ryzen-ai-5-pro-435.html
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/amdgpu: Add UMA carveout details 2026-01-05T21:59:58+00:00 Yo-Jung Leo Lin (AMD) Leo.Lin@amd.com 2025-12-12T07:59:17+00:00 5946dbe1c802efef3b12a4eecab1471f725f4ca9 Add documentation for the uma/carveout_options and uma/carveout attributes in sysfs Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add documentation for the uma/carveout_options and uma/carveout
attributes in sysfs

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Yo-Jung Leo Lin (AMD) <Leo.Lin@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Add documentation about ring buffer 2025-12-08T18:56:32+00:00 Rodrigo Siqueira siqueira@igalia.com 2025-11-19T00:45:54+00:00 03dc0a6cb6dc8a2ca0201acf599adb26b8c9423b AMDGPU heavily relies on ring buffers to manage its components; as a result, it has an elaborate mechanism of operation with multiple details around it. This commit introduces new documentation on ring buffers, detailing their management and expanding the explanation of Enforce isolation. Finally, this commit also adds the documentation available in the amdgpu_ring.c file to it. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
AMDGPU heavily relies on ring buffers to manage its components; as a
result, it has an elaborate mechanism of operation with multiple details
around it. This commit introduces new documentation on ring buffers,
detailing their management and expanding the explanation of Enforce
isolation. Finally, this commit also adds the documentation available in
the amdgpu_ring.c file to it.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Add more information about GC 2025-12-08T18:56:32+00:00 Rodrigo Siqueira siqueira@igalia.com 2025-11-19T00:45:53+00:00 03a48f07aa89ee72c2cfcc0be70858a745b2a573 This commit introduces set of information that details the different sets of schedulers available in the SE. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit introduces set of information that details the different
sets of schedulers available in the SE.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Expand generic block information 2025-12-08T18:56:32+00:00 Rodrigo Siqueira siqueira@igalia.com 2025-11-19T00:45:52+00:00 d68ba530ec79ec02c5432c3ae9c852081cc5ebb1 This commit expands the overall explanation about AMD GPU IPs by adding more details about their interconnection. Note that this commit includes a diagram that provides additional information. v2: fix up TMR - Trusted Memory Region Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
This commit expands the overall explanation about AMD GPU IPs by adding
more details about their interconnection. Note that this commit includes
a diagram that provides additional information.

v2: fix up TMR - Trusted Memory Region

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Add new glossary entries from UMR 2025-12-08T18:56:32+00:00 Rodrigo Siqueira siqueira@igalia.com 2025-11-19T00:45:51+00:00 e0f90f184d18c70c1b04e8b03a5243e275ce86f4 When using UMR, a dashboard is available that displays the CPC, CPF, CPG, TCP, and UTCL utilization. This commit introduces the meanings of those acronyms (and others) to the glossary to improve the comprehension of the UMR dashboard. Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Cc: Timur Kristóf <timur.kristof@gmail.com> Cc: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
When using UMR, a dashboard is available that displays the CPC, CPF,
CPG, TCP, and UTCL utilization. This commit introduces the meanings of
those acronyms (and others) to the glossary to improve the comprehension
of the UMR dashboard.

Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: Christian König <christian.koenig@amd.com>
Cc: Timur Kristóf <timur.kristof@gmail.com>
Cc: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation/gpu: Add PRT, PTE, PDE to amdgpu glossary (v2) 2025-12-08T18:56:31+00:00 Timur Kristóf timur.kristof@gmail.com 2025-11-19T09:25:44+00:00 c0d4cc9007971f7412f7ee4cbbe98b06b7da813f PRT = Partially Resident Texture (aka. sparse residency) PTE = Page Table Entry PDE = Page Directory Entry v2: - Add PDE Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
PRT = Partially Resident Texture (aka. sparse residency)
PTE = Page Table Entry
PDE = Page Directory Entry

v2:
- Add PDE

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Documentation: add initial documenation for user queues 2025-09-23T14:41:06+00:00 Alex Deucher alexander.deucher@amd.com 2025-05-02T20:22:45+00:00 0c1f3fe9a5f899ac95114e68959a35454af1523d Add an initial documentation page for user mode queues. Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> 
Add an initial documentation page for user mode queues.

Reviewed-by: Rodrigo Siqueira <siqueira@igalia.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>