linux.git/Documentation/driver-api/cxl, branch v6.17 Linux kernel source tree cxl: docs/devices Fix typos and clarify wording in device-types.rst 2025-06-30T23:36:06+00:00 Alok Tiwari alok.a.tiwari@oracle.com 2025-06-16T06:07:32+00:00 8ad85794be61e046697df8305de34a49791d2ed1 Fix several typos and improve comment clarity in the CXL device types docs: "w/" replaced with "with" "sill" -> "still" "The allows" -> "This allows" "capacity" corrected to "capable" "more devices" corrected to "more upstream devices" in MLD description These changes improve readability and enhance the documentation quality. [ dj: Fix up "one or more hosts" to "one or more upstream devices" from Gregory ] Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250616060737.1645393-1-alok.a.tiwari@oracle.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Fix several typos and improve comment clarity in the CXL device types
docs:
 "w/" replaced with "with"
 "sill" -> "still"
 "The allows" -> "This allows"
 "capacity" corrected to "capable"
 "more devices" corrected to "more upstream devices" in MLD description

These changes improve readability and enhance the documentation quality.

[ dj: Fix up "one or more hosts" to "one or more upstream devices" from
      Gregory ]

Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250616060737.1645393-1-alok.a.tiwari@oracle.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation: fix typo in CXL driver documentation 2025-06-30T23:36:06+00:00 Nai-Chen Cheng bleach1827@gmail.com 2025-06-10T17:31:52+00:00 7d14230db8a76c776985d510b9f27f66aedc7b14 Fix typo 'enumates' to 'enumerate' in CXL driver operation documentation to improve readability. Signed-off-by: Nai-Chen Cheng <bleach1827@gmail.com> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Reviewed-by: Li Ming <ming.li@zohomail.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250610173152.33566-1-bleach1827@gmail.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Fix typo 'enumates' to 'enumerate' in CXL driver operation
documentation to improve readability.

Signed-off-by: Nai-Chen Cheng <bleach1827@gmail.com>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Reviewed-by: Li Ming <ming.li@zohomail.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250610173152.33566-1-bleach1827@gmail.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation: cxl: fix typos and improve clarity in memory-devices.rst 2025-06-30T23:36:06+00:00 Alok Tiwari alok.a.tiwari@oracle.com 2025-06-09T17:10:48+00:00 5af29a583a17f9699b2a6de5e8148e8349d99a46 This patch corrects several typographical issues and improves phrasing in memory-devices.rst: - Fixes duplicate word ("1 one") and adjusts phrasing for clarity. - Adds missing hyphen in "on-device". - Corrects "a give memory device" to "a given memory device". - fix singular/plural "decoder resource" -> "decoder resources". - Clarifies "spans to Host Bridges" -> "spans two Host Bridges". - change "at a" -> "a" These changes improve readability and accuracy of the documentation. Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com> Link: https://patch.msgid.link/20250609171130.2375901-1-alok.a.tiwari@oracle.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
This patch corrects several typographical issues and improves phrasing
in memory-devices.rst:

- Fixes duplicate word ("1 one") and adjusts phrasing for clarity.
- Adds missing hyphen in "on-device".
- Corrects "a give memory device" to "a given memory device".
- fix singular/plural "decoder resource" -> "decoder resources".
- Clarifies "spans to Host Bridges" -> "spans two Host Bridges".
- change "at a" -> "a"

These changes improve readability and accuracy of the documentation.

Signed-off-by: Alok Tiwari <alok.a.tiwari@oracle.com>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
Link: https://patch.msgid.link/20250609171130.2375901-1-alok.a.tiwari@oracle.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation/driver-api/cxl: Introduce conventions.rst 2025-06-30T23:36:06+00:00 Dan Williams dan.j.williams@intel.com 2025-06-03T18:52:54+00:00 7ac6612d6b7994491ac410401ed2fbac2bdefc18 There exists shipping platforms that bend, break, or otherwise lean on ambiguities in the CXL specification. Without driver changes to accommodate these deviations, end users are left without CXL subsystem RAS features. Specifically, provisioning, error translation, and other flows require the CXL subsystem to understand the platforms CXL topology beyond undecorated memory address ranges. Those isolated compatibility problems risk growing into deeper upstream maintenance burden if different platform vendors arrive at diverging solutions. For example, there are multiple options for resolving low-memory-mmio intersecting large-interleave-ways CXL windows. Linux should only entertain one solution to that problem. Now, with the ACPI Specification Working Group, situations like this would be resolved with the "Code First ECN" process to codify Linux expectations in a specification. In the absence of such a process for the CXL specification, create a file in Linux documentation to detail the motivations, assumptions, tradeoffs, and proposals for amending specification language. The goal is to capture the issues such that platform vendors arrive at compatible solutions for these problems and serve as a repository for potential specification updates. The expectation is to update conventions.rst along with CXL subsystem code changes to accommodate the platform topology. [ dj: Rebased against v6.16-rc1 ] Signed-off-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Reviewed-by: Robert Richter <rrichter@amd.com> Link: https://patch.msgid.link/20250603185254.3730099-1-dan.j.williams@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
There exists shipping platforms that bend, break, or otherwise lean on
ambiguities in the CXL specification. Without driver changes to accommodate
these deviations, end users are left without CXL subsystem RAS features.
Specifically, provisioning, error translation, and other flows require the
CXL subsystem to understand the platforms CXL topology beyond undecorated
memory address ranges.

Those isolated compatibility problems risk growing into deeper upstream
maintenance burden if different platform vendors arrive at diverging
solutions. For example, there are multiple options for resolving
low-memory-mmio intersecting large-interleave-ways CXL windows. Linux
should only entertain one solution to that problem.

Now, with the ACPI Specification Working Group, situations like this would
be resolved with the "Code First ECN" process to codify Linux expectations
in a specification. In the absence of such a process for the CXL
specification, create a file in Linux documentation to detail the
motivations, assumptions, tradeoffs, and proposals for amending
specification language.

The goal is to capture the issues such that platform vendors arrive at
compatible solutions for these problems and serve as a repository for
potential specification updates. The expectation is to update
conventions.rst along with CXL subsystem code changes to accommodate the
platform topology.

[ dj: Rebased against v6.16-rc1 ]

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Reviewed-by: Robert Richter <rrichter@amd.com>
Link: https://patch.msgid.link/20250603185254.3730099-1-dan.j.williams@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: doc/linux/access-coordinates Update access coordinates calculation methods 2025-05-15T23:39:13+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:23+00:00 fc78561595e2fc6ceb8da56b083847227ba9320e Add documentation on how to calculate the access coordinates for a given CXL region in detail. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add documentation on how to calculate the access coordinates for a given
CXL region in detail.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/acpi/srat Add generic target documentation 2025-05-15T23:39:13+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:22+00:00 1ce91b37b2661ebeca71982eadf3e3d5e0584a2f Add description in the SRAT document to describe the Generic Port Affinity sub-table. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add description in the SRAT document to describe the Generic Port
Affinity sub-table.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/cdat reference documentation 2025-05-15T23:39:12+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:21+00:00 49cee8fe5e6c6af2c6a76448840ae2eef9641084 Add documentation for CDAT structures for CXL usages. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add documentation for CDAT structures for CXL usages.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation: Update the CXL Maturity Map 2025-05-15T23:34:26+00:00 Alison Schofield alison.schofield@intel.com 2025-05-12T21:42:22+00:00 f97bdc61c76f654effa7b78e10338e64794da9fd Changes for extended-linear cache, hetero-interleave, and HPA->DPA address translation. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Changes for extended-linear cache, hetero-interleave, and HPA->DPA
address translation.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: Sync up the driver-api/cxl documentation 2025-05-13T22:12:15+00:00 Alison Schofield alison.schofield@intel.com 2025-05-13T21:58:09+00:00 d542461211543522daecb34b7972d8ac1044bc97 pmem.c regs.c mbox.c identifiers were missing. Add them to memory-devices.rst following their respective DOC comment includes. Two acpi.c identifiers were available, but not used in kernel-doc's: 1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx complaint on the ascii art by escaping it. 2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst. core/features.c is new. Add a "DOC: cxl features" comment to the source and identifiers to memory_devices.rst. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
pmem.c regs.c mbox.c identifiers were missing. Add them to
memory-devices.rst following their respective DOC comment includes.

Two acpi.c identifiers were available, but not used in kernel-doc's:
1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx
complaint on the ascii art by escaping it.
2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst.

core/features.c is new. Add a "DOC: cxl features" comment to the
source and identifiers to memory_devices.rst.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs - add self-referencing cross-links 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:34+00:00 dba600d0f2e9d2dea53891d95f1ff38d3e089275 Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add some crosslinks between pages in the CXL docs - mostly to the
ACPI tables.

Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>