linux.git/Documentation/driver-api/cxl, branch v6.16 Linux kernel source tree cxl: doc/linux/access-coordinates Update access coordinates calculation methods 2025-05-15T23:39:13+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:23+00:00 fc78561595e2fc6ceb8da56b083847227ba9320e Add documentation on how to calculate the access coordinates for a given CXL region in detail. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add documentation on how to calculate the access coordinates for a given
CXL region in detail.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-4-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/acpi/srat Add generic target documentation 2025-05-15T23:39:13+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:22+00:00 1ce91b37b2661ebeca71982eadf3e3d5e0584a2f Add description in the SRAT document to describe the Generic Port Affinity sub-table. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add description in the SRAT document to describe the Generic Port
Affinity sub-table.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-3-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/platform/cdat reference documentation 2025-05-15T23:39:12+00:00 Dave Jiang dave.jiang@intel.com 2025-05-15T00:09:21+00:00 49cee8fe5e6c6af2c6a76448840ae2eef9641084 Add documentation for CDAT structures for CXL usages. Reviewed-by: Gregory Price <gourry@gourry.net> Reviewed-by: Alison Schofield <alison.schofield@intel.com> Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add documentation for CDAT structures for CXL usages.

Reviewed-by: Gregory Price <gourry@gourry.net>
Reviewed-by: Alison Schofield <alison.schofield@intel.com>
Link: https://patch.msgid.link/20250515000923.2590820-2-dave.jiang@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
Documentation: Update the CXL Maturity Map 2025-05-15T23:34:26+00:00 Alison Schofield alison.schofield@intel.com 2025-05-12T21:42:22+00:00 f97bdc61c76f654effa7b78e10338e64794da9fd Changes for extended-linear cache, hetero-interleave, and HPA->DPA address translation. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Dave Jiang <dave.jiang@intel.com> Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Changes for extended-linear cache, hetero-interleave, and HPA->DPA
address translation.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Dave Jiang <dave.jiang@intel.com>
Link: https://patch.msgid.link/20250512214225.1389484-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: Sync up the driver-api/cxl documentation 2025-05-13T22:12:15+00:00 Alison Schofield alison.schofield@intel.com 2025-05-13T21:58:09+00:00 d542461211543522daecb34b7972d8ac1044bc97 pmem.c regs.c mbox.c identifiers were missing. Add them to memory-devices.rst following their respective DOC comment includes. Two acpi.c identifiers were available, but not used in kernel-doc's: 1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx complaint on the ascii art by escaping it. 2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst. core/features.c is new. Add a "DOC: cxl features" comment to the source and identifiers to memory_devices.rst. Signed-off-by: Alison Schofield <alison.schofield@intel.com> Reviewed-by: Ira Weiny <ira.weiny@intel.com> Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
pmem.c regs.c mbox.c identifiers were missing. Add them to
memory-devices.rst following their respective DOC comment includes.

Two acpi.c identifiers were available, but not used in kernel-doc's:
1) Add add_cxl_resources to memory-devices.rst and fix up the Sphinx
complaint on the ascii art by escaping it.
2) Add cxl_acpi_evaluate_qtg_dsm to access-coordinates.rst.

core/features.c is new. Add a "DOC: cxl features" comment to the
source and identifiers to memory_devices.rst.

Signed-off-by: Alison Schofield <alison.schofield@intel.com>
Reviewed-by: Ira Weiny <ira.weiny@intel.com>
Link: https://patch.msgid.link/20250513215813.1419645-1-alison.schofield@intel.com
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs - add self-referencing cross-links 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:34+00:00 dba600d0f2e9d2dea53891d95f1ff38d3e089275 Add some crosslinks between pages in the CXL docs - mostly to the ACPI tables. Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com> Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add some crosslinks between pages in the CXL docs - mostly to the
ACPI tables.

Suggested-by: Bagas Sanjaya <bagasdotme@gmail.com>
Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-18-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/allocation/hugepages 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:33+00:00 df63e0120b5ee35896b05a5d96d686105509c3f7 Add docs on how CXL capacity interacts with CMA and HugeTLB allocation interfaces. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-17-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Add docs on how CXL capacity interacts with CMA and HugeTLB allocation
interfaces.

Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-17-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/allocation/reclaim 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:32+00:00 f109e77dde6e52439dce9fca19a0121c7cd04424 Document a bit about how reclaim interacts with various CXL configurations. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-16-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Document a bit about how reclaim interacts with various CXL
configurations.

Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-16-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/allocation/page-allocator 2025-05-13T20:07:46+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:31+00:00 419dc40b82374cc7c417f0af613b9e6ea1d34095 Document some interesting interactions that occur when exposing CXL memory capacity to page allocator. Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-15-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Document some interesting interactions that occur when exposing CXL
memory capacity to page allocator.

Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-15-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>
cxl: docs/allocation/dax 2025-05-13T20:07:45+00:00 Gregory Price gourry@gourry.net 2025-05-12T16:21:30+00:00 78ab67510ed9933bb3622d313dde93c6739d37ae Small example of accessing CXL memory capacity via DAX device Signed-off-by: Gregory Price <gourry@gourry.net> Link: https://patch.msgid.link/20250512162134.3596150-14-gourry@gourry.net Signed-off-by: Dave Jiang <dave.jiang@intel.com> 
Small example of accessing CXL memory capacity via DAX device

Signed-off-by: Gregory Price <gourry@gourry.net>
Link: https://patch.msgid.link/20250512162134.3596150-14-gourry@gourry.net
Signed-off-by: Dave Jiang <dave.jiang@intel.com>