linux.git/Documentation/devicetree/bindings/timer, branch v4.13-rc2

Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

2017-07-04T21:37:25+00:00

Pull ARM device-tree updates from Arnd Bergmann:
 "Device-tree continues to see lots of updates. The majority of patches
  here are smaller changes for new hardware on existing platforms, and
  there are a few larger changes worth pointing out.

  New machines:

   - The new Action Semi S500 platform is added along with initial
     support for the LeMaker Guitar board.

   - STM32 gains support for three new boards: stm32h743-disco,
     stm32f746-disco, and stm32f769-disco, along with new device support
     for the existing stm32f429 boards.

   - Renesas adds two new boards, the tiny GR-Peach based on RZ/A1H with
     10MB on-chip SRAM, and the iWave G20D-Q7 System-on-Module plus
     board.

   - On Marvell "mvebu", we gain support for the Linksys WRT3200ACM
     wireless router.

   - For NXP i.MX, we gain support for the Gateworks Ventana GW5600 and
     the Technexion Pico i.MX7D single-board computers.

   - The BeagleBone Blue is added for OMAP, it's the latest variation of
     the popular Beaglebone Black single-board computer.

   - The Allwinner based Lichee Pi Zero and NanoPi M1 Plus boards are
     added, these are the latest variations of a seemingly endless
     supply of similar single-board computers.

  Other updates:

   - Linus Walleij improves support for the "Faraday" based SoC
     platforms from various SoC makers (Moxart, Aspeed, Gemini)

   - The ARM Mali GPU is now describe on Rockchips SoCs

   - Mediatek MT7623 is extended significantly, making it much more
     useful.

   - Lots of individual updates on Renesas, OMAP, Rockchips, Broadcom,
     Allwinner, Qualcomm, iMX

   - For Amlogic, the clock support is extended a lot on meson8b.

   - We now build the devicetree file for the Raspberry Pi 3 on 32-bit
     ARM, in addition to the existing ARM64 support, to help users
     wanting to run a 32-bit system on it"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (345 commits)
  ARM: dts: socfpga: set the i2c frequency
  ARM: dts: socfpga: Add second ethernet alias to VINING FPGA
  ARM: dts: socfpga: Drop LED node from VINING FPGA
  ARM: dts: socfpga: Remove I2C EEPROMs from VINING FPGA
  ARM: dts: socfpga: Enable QSPI support on VINING FPGA
  ARM: dts: socfpga: Fix the ethernet clock phandle
  ARM: pxa: Use - instead of @ for DT OPP entries
  ARM: dts: owl-s500: Add SPS node
  ARM: dts: owl-s500: Set CPU enable-method
  dt-bindings: arm: cpus: Add S500 enable-method
  ARM: dts: Add Actions Semi S500 and LeMaker Guitar
  dt-bindings: arm: Document Actions Semi S900
  dt-bindings: timer: Document Owl timer
  ARM: dts: imx6q-cm-fx6: add sdio wifi/bt nodes
  dt-bindings: arm: Document Actions Semi S500
  dt-bindings: Add vendor prefix for Actions Semi
  ARM: dts: turris-omnia: Add generic compatible string for I2C EEPROM
  ARM: dts: mvebu: add support for Linksys WRT3200ACM (Rango)
  ARM: dts: armada-385-linksys: fixup button node names
  ARM: dts: armada-385-linksys: group pins in pinctrl
  ...

dt-bindings: timer: Document Owl timer

2017-06-18T19:19:04+00:00

The Actions Semi S500 SoC contains a timer block with two 2 Hz and two
32-bit timers. The S900 SoC timer block has four 32-bit timers.

Acked-by: Rob Herring 
Signed-off-by: Andreas Färber

clocksource/drivers/fttmr010: Add AST2500 compatible string

2017-06-12T08:45:23+00:00

Also clean up space-before-tab issues in the documentation.

Signed-off-by: Andrew Jeffery 
Acked-by: Joel Stanley 
Acked-by: Rob Herring 
Reviewed-by: Linus Walleij 
Signed-off-by: Daniel Lezcano

clocksource/drivers/fttmr010: Merge FTTMR010 DT bindings

2017-06-12T08:13:58+00:00

This merges the Moxa and FTTMR010 device tree bindings into the
Faraday binding document to avoid confusion.

The FTTMR010 is the IP block used by these SoCs, in vanilla
or modified variant.

The Aspeed variant is modified such that it is no longer fully
register-compatible with FTTMR010 so for this reason it is not
listed with two compatible strings, instead just one.

Cc: Joel Stanley 
Tested-by: Jonas Jensen 
Signed-off-by: Linus Walleij 
Acked-by: Rob Herring 
Acked-by: Joel Stanley 
Signed-off-by: Daniel Lezcano

clocksource: Augment bindings for Faraday timer

2017-04-07T14:23:07+00:00

It turns out that the Cortina Gemini timer block is just a
standard IP block from Faraday Technology named FTTMR010.

In order to make things clear and understandable, we rename the
bindings with a Faraday compatible as primary and the Cortina
gemini as a more specific case.

For the plain Faraday timer we require two clock references,
while the Gemini can keep it's syscon lookup pattern.

Signed-off-by: Linus Walleij 
Signed-off-by: Daniel Lezcano 
Acked-by: Rob Herring

dt-bindings: Clarify compatible property for rockchip timers

2017-04-07T14:23:04+00:00

Make all properties description in form '"rockchip,-timer",
"rockchip,rk3288-timer"' for all chips found in linux kernel.

Suggested-by: Heiko Stübner 
Signed-off-by: Alexander Kochetkov 
Acked-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Daniel Lezcano

clocksource/drivers/ostm: Document renesas-ostm timer DT bindings

2017-02-07T19:58:30+00:00

Signed-off-by: Chris Brandt 
Reviewed-by: Geert Uytterhoeven 
Acked-by: Rob Herring 
Signed-off-by: Daniel Lezcano

clocksource: add DT bindings for Cortina Gemini

2017-02-07T19:58:30+00:00

This adds device tree bindings for the Cortina Systems Gemini
timer block used in these SoCs.

Cc: Janos Laube 
Cc: Paulius Zaleckas 
Cc: Hans Ulli Kroll 
Cc: Florian Fainelli 
Cc: devicetree@vger.kernel.org
Signed-off-by: Linus Walleij 
Acked-by: Rob Herring 
Signed-off-by: Daniel Lezcano

clocksource: Add clockevent support to NPS400 driver

2016-11-30T19:54:25+00:00

Till now we used clockevent from generic ARC driver.
This was enough as long as we worked with simple multicore SoC.
When we are working with multithread SoC each HW thread can be
scheduled to receive timer interrupt using timer mask register.
This patch will provide a way to control clock events per HW thread.

The design idea is that for each core there is dedicated register
(TSI) serving all 16 HW threads.
The register is a bitmask with one bit for each HW thread.
When HW thread wants that next expiration of timer interrupt will
hit it then the proper bit should be set in this dedicated register.
When timer expires all HW threads within this core which their bit
is set at the TSI register will be interrupted.

Driver can be used from device tree by:
compatible = "ezchip,nps400-timer0" <-- for clocksource
compatible = "ezchip,nps400-timer1" <-- for clockevent

Note that name convention for timer0/timer1 was taken from legacy
ARC design. This design is our base before adding HW threads.
For backward compatibility we keep "ezchip,nps400-timer" for clocksource

Signed-off-by: Noam Camus 
Acked-by: Daniel Lezcano 
Acked-by: Rob Herring

of: Add J-Core timer bindings

2016-10-20T18:10:17+00:00

Signed-off-by: Rich Felker 
Acked-by: Rob Herring 
Cc: Mark Rutland 
Cc: devicetree@vger.kernel.org
Cc: linux-sh@vger.kernel.org
Cc: Daniel Lezcano 
Cc: Rob Herring 
Link: http://lkml.kernel.org/r/8b107c292ed8cf8eed0fa283071fc8a930098628.1476393790.git.dalias@libc.org
Signed-off-by: Thomas Gleixner