linux.git/Documentation/devicetree/bindings/spi, branch master Linux kernel source tree spi: dt-bindings: spi-qpic-snand: Add ipq5210 compatible 2026-05-26T18:38:46+00:00 Varadarajan Narayanan varadarajan.narayanan@oss.qualcomm.com 2026-05-14T06:45:31+00:00 60474437af5fe12abd20607766c809e0ad4e7245 Since the QPIC-SPI-NAND flash controller present in ipq5210 is the same as the one found in ipq9574, document the ipq5210 compatible and with ipq9574 as the fallback. Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com> Link: https://patch.msgid.link/20260514-ipq5210-nand-v1-1-cbdd7492e826@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Since the QPIC-SPI-NAND flash controller present in ipq5210 is the same
as the one found in ipq9574, document the ipq5210 compatible and with
ipq9574 as the fallback.

Signed-off-by: Varadarajan Narayanan <varadarajan.narayanan@oss.qualcomm.com>
Link: https://patch.msgid.link/20260514-ipq5210-nand-v1-1-cbdd7492e826@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dt-bindings: fsl-qspi: support SpacemiT K3 2026-05-21T20:56:07+00:00 Zhengyu He hezhy472013@gmail.com 2026-05-21T14:44:45+00:00 27cd2dde35b2c3b8659fa18f6a935c61fedee5c1 Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding. K3 and K1 use the same QSPI controller, so document the K3 compatible with "spacemit,k1-qspi" as fallback. Signed-off-by: Cody Kang <cody.kang.hk@outlook.com> Signed-off-by: Zhengyu He <hezhy472013@gmail.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Add the SpacemiT K3 QSPI compatible to the fsl-qspi binding.

K3 and K1 use the same QSPI controller, so document the K3 compatible
with "spacemit,k1-qspi" as fallback.

Signed-off-by: Cody Kang <cody.kang.hk@outlook.com>
Signed-off-by: Zhengyu He <hezhy472013@gmail.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260521-k3-pico-itx-qspi-v2-for-next-20260521-v2-1-52bce26e5fd8@gmail.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dt-bindings: fsl: Correct GPIO flags in the example 2026-04-14T11:56:00+00:00 Krzysztof Kozlowski krzysztof.kozlowski@oss.qualcomm.com 2026-04-13T08:59:48+00:00 ebeef57b7ba92ff5b4edcd14a34b30b9645871db IRQ_TYPE_xxx flags are not correct in the context of GPIO flags. These are simple defines so they could be used in DTS but they will not have the same meaning: IRQ_TYPE_EDGE_RISING = 1 = GPIO_ACTIVE_LOW. Correct the example DTS to use proper flags for chip select GPIOs, assuming the author of the code wanted similar logical behavior: IRQ_TYPE_EDGE_RISING => GPIO_ACTIVE_HIGH Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260413085947.51047-2-krzysztof.kozlowski@oss.qualcomm.com Signed-off-by: Mark Brown <broonie@kernel.org> 
IRQ_TYPE_xxx flags are not correct in the context of GPIO flags.
These are simple defines so they could be used in DTS but they will not
have the same meaning: IRQ_TYPE_EDGE_RISING = 1 = GPIO_ACTIVE_LOW.

Correct the example DTS to use proper flags for chip select GPIOs,
assuming the author of the code wanted similar logical behavior:

  IRQ_TYPE_EDGE_RISING => GPIO_ACTIVE_HIGH

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260413085947.51047-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Mark Brown <broonie@kernel.org>
Add Renesas RZ/G3L RSPI support 2026-04-08T14:57:55+00:00 Mark Brown broonie@kernel.org 2026-04-08T14:57:55+00:00 2c9e7a5f2e3f398213c0c122c18ffa2f4e192457 Biju <biju.das.au@gmail.com> says: This patch series adds binding and driver support for RSPI IP found on the RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks compared to 3 on RZ/V2H. Link: https://patch.msgid.link/20260408085418.18770-1-biju.das.jz@bp.renesas.com 
Biju <biju.das.au@gmail.com> says:

This patch series adds binding and driver support for RSPI IP found on the
RZ/G3L SoC. The RSPI is compatible with RZ/V2H RSPI, but has 2 clocks
compared to 3 on RZ/V2H.

Link: https://patch.msgid.link/20260408085418.18770-1-biju.das.jz@bp.renesas.com
spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3L SoC 2026-04-08T14:57:52+00:00 Biju Das biju.das.jz@bp.renesas.com 2026-04-08T08:54:14+00:00 5277c291968d87c6a093f50ef489df9d52cb3ca9 Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Link: https://patch.msgid.link/20260408085418.18770-2-biju.das.jz@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Document RSPI IP found on the RZ/G3L SoC. The RSPI IP is compatible with
the RZ/V2H RSPI IP, but has 2 clocks compared to 3 on RZ/V2H.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://patch.msgid.link/20260408085418.18770-2-biju.das.jz@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dt-bindings: renesas,rzv2h-rspi: Document RZ/G3E SoC support 2026-03-18T17:39:35+00:00 Tommaso Merciai tommaso.merciai.xr@bp.renesas.com 2026-02-17T16:23:47+00:00 5b7ac8ca0eae522735d24f7c5c2296c8094328b1 Document the RSPI controller on the Renesas RZ/G3E SoC. The block is compatible with the RSPI implementation found on the RZ/V2H(P) family. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/f6b43f0dc64e13b1c9942c164dea30002d4c4466.1771344527.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Document the RSPI controller on the Renesas RZ/G3E SoC. The block is
compatible with the RSPI implementation found on the RZ/V2H(P) family.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/f6b43f0dc64e13b1c9942c164dea30002d4c4466.1771344527.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dt-bindings: renesas,rzv2h-rspi: Document dmas property 2026-03-18T17:39:34+00:00 Tommaso Merciai tommaso.merciai.xr@bp.renesas.com 2026-02-17T16:23:46+00:00 c2edd7841f58cf228347b91256f0d9efcc1a1f50 Document the dmas property to state it must be specified as TX/RX DMA specifier pairs. This clarifies the expected ordering and improves binding readability without changing behavior. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://patch.msgid.link/ea6ed3b82c5a326732adfc0fcdb2922bfcad2591.1771344527.git.tommaso.merciai.xr@bp.renesas.com Signed-off-by: Mark Brown <broonie@kernel.org> 
Document the dmas property to state it must be specified as TX/RX DMA
specifier pairs.
This clarifies the expected ordering and improves binding readability
without changing behavior.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://patch.msgid.link/ea6ed3b82c5a326732adfc0fcdb2922bfcad2591.1771344527.git.tommaso.merciai.xr@bp.renesas.com
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: controller registration fixes 2026-03-16T18:36:09+00:00 Mark Brown broonie@kernel.org 2026-03-16T18:36:09+00:00 29a80e6c3a38f0c533b5a17ae6862886d6322510 Johan Hovold <johan@kernel.org> says: This series fixes a few issues related to controller registration found through inspection. 
Johan Hovold <johan@kernel.org> says:

This series fixes a few issues related to controller registration found
through inspection.
spi: dt-bindings: sun6i: Allow Dual SPI and Quad SPI for newer SoCs 2026-03-11T11:34:10+00:00 Chen-Yu Tsai wens@kernel.org 2026-03-02T15:35:56+00:00 743956bb9990214ff1dac66ef59e27221dc3c2d8 Support for Dual SPI and Quad SPI was added to the Linux driver in commit 0605d9fb411f ("spi: sun6i: add quirk for dual and quad SPI modes support") and commit 25453d797d7a ("spi: sun6i: add dual and quad SPI modes support for R329/D1/R528/T113s"). However the binding was never updated to allow these modes. Allow them by adding 2 and 4 to the allowed bus widths for the newer variants. While at it, also add 0 to the allowed bus widths. This signals that RX or TX is not available, i.e. the MISO or MOSI pin is disconnected. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Chen-Yu Tsai <wens@kernel.org> Link: https://patch.msgid.link/20260302153559.3199783-2-wens@kernel.org Signed-off-by: Mark Brown <broonie@kernel.org> 
Support for Dual SPI and Quad SPI was added to the Linux driver in
commit 0605d9fb411f ("spi: sun6i: add quirk for dual and quad SPI modes
support") and commit 25453d797d7a ("spi: sun6i: add dual and quad SPI
modes support for R329/D1/R528/T113s").

However the binding was never updated to allow these modes. Allow them
by adding 2 and 4 to the allowed bus widths for the newer variants.

While at it, also add 0 to the allowed bus widths. This signals that
RX or TX is not available, i.e. the MISO or MOSI pin is disconnected.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Chen-Yu Tsai <wens@kernel.org>
Link: https://patch.msgid.link/20260302153559.3199783-2-wens@kernel.org
Signed-off-by: Mark Brown <broonie@kernel.org>
spi: dt-bindings: mpfs-spi: remove clock-names 2026-03-03T17:34:55+00:00 Conor Dooley conor.dooley@microchip.com 2026-03-03T16:41:52+00:00 96f06d055ca03d1dfb5830fd07ff6eadbd66264c This binding documented clock-names, but never bothered to document what the name should be, rendering the property useless to software. It's not a required property, so it can just be removed without harming any software that conjured up it's own name for the clock, as they could not rely on it being there to begin with. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Link: https://patch.msgid.link/20260303-spoils-snowbird-99f6e3a2dae3@spud Signed-off-by: Mark Brown <broonie@kernel.org> 
This binding documented clock-names, but never bothered to document what
the name should be, rendering the property useless to software. It's not
a required property, so it can just be removed without harming any
software that conjured up it's own name for the clock, as they could not
rely on it being there to begin with.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260303-spoils-snowbird-99f6e3a2dae3@spud
Signed-off-by: Mark Brown <broonie@kernel.org>