linux.git/Documentation/devicetree/bindings/soc, branch master Linux kernel source tree Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2026-08-26T18:14:30+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-26T18:14:30+00:00 502d45774af09f1c681c754c4b7cdfb5d7f72fd9 Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include <linux/mod_devicetable.h> clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... 
Pull clk updates from Stephen Boyd:
 "Mostly the usual clk driver updates and new SoC additions plus
  non-critical data fixes for things that weren't used yet.

  One thing that's new here in the core is SSC spread spectrum support
  (SSC) in the clk provider API. The idea is that DT authors will
  configure SSC for certain clks and they'll be configured at clk
  provider registration time or when a consumer device is probed,
  similar to how we handle assigned clk rates or parents.

  On the clk driver side we have Qualcomm adding almost half the diff
  because they add support for 4 different SoCs and then a long tail of
  other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more
  SoC support this time around. Luckily it's mostly clk data for these
  new SoCs because the actual clk_ops are already there. Beyond the new
  drivers we get all the little fixups for more compilation coverage or
  usage of more modern APIs. That all looks normal.

  Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to
  help out with maintaining the clk subsystem. The current working model
  is already semi-distributed in that silicon vendors typically take
  care of their drivers and send me pull requests but I'm becoming a
  bottleneck for new drivers and core framework review because this has
  become a 100% volunteer effort on my part.

  Mike is stepping down after all these years (thanks Mike!) and that
  jump started the conversation around finding co-maintainers. Brian and
  Jerome have graciously offered to help me with the work load, meaning
  in the future they'll be sending pull requests and committing directly
  to the clk.git tree. They've both been around on the list for a while,
  I've met them both in person, and they've been making changes to the
  core clk framework along with helping review patches so I'm pretty
  confident this will work well.

  Core:
   - devm_clk_bulk_get_enable() consumer API
   - devm_clk_hw_register_composite_pdata() provider API
   - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs
   - Divider clk rounding improved (and tested)

  New Drivers:
   - Cix Sky1 audio subsystem (AUDSS)
   - UltraRISC DP1000
   - MediaTek MT8173 MFG_TOP
   - Si549
   - Aspeed AST2700 PECI
   - Airoha EN7523 PCIe
   - Rockchip RV1106
   - Mobileye EyeQ7H
   - Qualcomm Maili GCC, TCSR, RPMh, and video clks
   - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks
   - Qualcomm Nord display and graphics clks
   - Qualcomm Glymur camera and EVA clks
   - Qualcomm Hawi video clks
   - Amlogic A9 AO and peripheral clks
   - Renesas R-Car X5H (R8A78000) CPG"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits)
  clk: microchip: mpfs: fix regmap_update_bits() mask/val order
  clk: visconti: Make sure clk_init_data is fully initialized
  clk: ti: Make sure clk_init_data is fully initialized
  MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
  Drop Michael Turquette's clk maintainer entry
  clk: ti: composite: resolve parent clocks by DT index, not by name
  clk: ti: mux: resolve parent clocks by DT index, not by name
  clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
  dt-bindings: clock: ti,keystone-gate: Convert to DT schema
  dt-bindings: clock: ti: Convert APLL clock to DT schema
  clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
  dt-bindings: clock: ti,clockdomain: Convert to DT schema
  dt-bindings: clock: Correct white-space style
  clk: samsung: Don't include <linux/mod_devicetable.h>
  clk: at91: Read "reg" with helper
  clk: renesas: Add R-Car X5H CPG driver
  clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
  clk: rockchip: Add clock controller for the RV1106
  dt-bindings: clock: rockchip: Add RV1106 CRU support
  dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
  ...
Merge branches 'clk-pile' and 'clk-microchip' into clk-next 2026-08-20T23:51:47+00:00 Stephen Boyd sboyd@kernel.org 2026-08-20T23:51:47+00:00 dd8eb789f18c4c600f28e61176a02bcf3b790117 * clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper 
* clk-pile: (111 commits)
  clk: microchip: mpfs: fix regmap_update_bits() mask/val order
  clk: visconti: Make sure clk_init_data is fully initialized
  clk: ti: Make sure clk_init_data is fully initialized
  MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
  Drop Michael Turquette's clk maintainer entry
  clk: ti: composite: resolve parent clocks by DT index, not by name
  clk: ti: mux: resolve parent clocks by DT index, not by name
  clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
  dt-bindings: clock: ti,keystone-gate: Convert to DT schema
  dt-bindings: clock: ti: Convert APLL clock to DT schema
  clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
  dt-bindings: clock: ti,clockdomain: Convert to DT schema
  dt-bindings: clock: Correct white-space style
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  ...

* clk-microchip:
  clk: at91: Read "reg" with helper
Merge tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2026-08-19T17:32:34+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-19T17:32:34+00:00 c6cf4441a3a05bb7273ed022f3e56c4fc591da08 Pull devicetree updates from Rob Herring: - Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style * tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits) dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible dtc: dt-check-style: Simplify setting depth of DtsLine dtc: dt-check-style: Add missing /dts-v1/ to few test cases dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema media: dt-bindings: ti,da850-vpif: Convert to dt-schema dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer dt-bindings: arm: omap: Convert L4 interconnect to DT schema dt-bindings: power: Convert TI SmartReflex to DT schema of: reserved_mem: Introduce devres-managed initialization function dt-bindings: interrupt-controller: Add StarFive JHB100 plic dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller dt-bindings: Correct white-space style dt-bindings: fix typos and brackets docs: dt: submitting-patches: Mention expectation about dt-check-style docs: dt: maintainer: Add Devicetree and OF maintainer profile document docs: dt: writing-schema: Extend expectations about example part of binding dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU of: base: Handle optional argument in of_parse_phandle_with_args_map() dt-bindings: update Sudeep Holla's email address ... 
Pull devicetree updates from Rob Herring:

 - Add a DT maintainer profile document

 - Various dt-check-style improvements

 - Add a devres managed reserved memory region init function

 - Print node name on any skipped reserved memory regions

 - Correctly handle optional argument in
   of_parse_phandle_with_args_map()

 - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI
   SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI
   DA8XX MSTPRI bus, and Xen VM bindings to DT schema format

 - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller,
   MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and
   QCom Shikra SCM firmware

 - A couple of syntax fixes found using PoC Rust implementation of
   dtschema tools

 - Clean-ups for typos, brackets, incorrect "::" usages, and
   white-space style

* tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits)
  dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible
  dtc: dt-check-style: Simplify setting depth of DtsLine
  dtc: dt-check-style: Add missing /dts-v1/ to few test cases
  dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema
  media: dt-bindings: ti,da850-vpif: Convert to dt-schema
  dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax
  dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer
  dt-bindings: arm: omap: Convert L4 interconnect to DT schema
  dt-bindings: power: Convert TI SmartReflex to DT schema
  of: reserved_mem: Introduce devres-managed initialization function
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller
  dt-bindings: Correct white-space style
  dt-bindings: fix typos and brackets
  docs: dt: submitting-patches: Mention expectation about dt-check-style
  docs: dt: maintainer: Add Devicetree and OF maintainer profile document
  docs: dt: writing-schema: Extend expectations about example part of binding
  dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
  of: base: Handle optional argument in of_parse_phandle_with_args_map()
  dt-bindings: update Sudeep Holla's email address
  ...
Merge tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2026-08-19T02:40:29+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-19T02:40:29+00:00 368cf60c36a3a311474de08e52dc6314df3b06ce Pull SoC driver updates from Arnd Bergmann: "The SoC driver changes once more consist of many small fixes and cleanups, that are to a large part the result of automated testing. On platform specific drivers, this includes SoC specific code for xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung, rockchip, renesas, ixp4xx. In firmware drivers, we see a similar picture for SCMI and qcomtee. Aside from these, we see actual new hardware support in a few areas: - The Apple platform gets a new driver for low power states - Updates to Qualcomm platform drivers add several new hardware specific features and additional SoCs. - Amlogic SoC support for A1 and T7 is added - The Mediatek MMSYS driver is refactored as a cleanup" * tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits) soc: qcom: make QCOM_PDR_MSG selectable soc: qcom: ubwc: Fix missing include soc: qcom: ubwc: Fix link error when QCOM_SMEM=n media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850 firmware: xilinx: Clear firmware notifiers across kexec transitions firmware: xilinx: Release all peripheral devices from firmware firmware: xilinx: Add support to clear EL3 PM state firmware: xilinx: Propagate actual error from feature check firmware: xilinx: Use TF-A feature check for TF-A-specific APIs bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state ... 
Pull SoC driver updates from Arnd Bergmann:
 "The SoC driver changes once more consist of many small fixes and
  cleanups, that are to a large part the result of automated testing.

  On platform specific drivers, this includes SoC specific code for
  xilinx, freescale/nxp, qualcomm, TI, aspeed, omap, tegra, samsung,
  rockchip, renesas, ixp4xx. In firmware drivers, we see a similar
  picture for SCMI and qcomtee.

  Aside from these, we see actual new hardware support in a few areas:

   - The Apple platform gets a new driver for low power states

   - Updates to Qualcomm platform drivers add several new hardware
     specific features and additional SoCs.

   - Amlogic SoC support for A1 and T7 is added

   - The Mediatek MMSYS driver is refactored as a cleanup"

* tag 'soc-drivers-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (157 commits)
  soc: qcom: make QCOM_PDR_MSG selectable
  soc: qcom: ubwc: Fix missing include
  soc: qcom: ubwc: Fix link error when QCOM_SMEM=n
  media: iris: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
  drm/msm: Guard the QCOM_UBWC_CONFIG select with QCOM_SMEM
  dt-bindings: arm: qcom,ids: Add SoC ID for Snapdragon SDM 850
  firmware: xilinx: Clear firmware notifiers across kexec transitions
  firmware: xilinx: Release all peripheral devices from firmware
  firmware: xilinx: Add support to clear EL3 PM state
  firmware: xilinx: Propagate actual error from feature check
  firmware: xilinx: Use TF-A feature check for TF-A-specific APIs
  bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
  soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
  phy: lynx-10g: use RCW override procedure for dynamic protocol change
  soc: fsl: guts: implement the RCW override procedure
  dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
  soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
  soc: fsl: guts: make it easier to determine on which SoC we are running
  soc: fsl: guts: add a central fsl_guts_read() function
  soc: fsl: guts: add a global structure to hold state
  ...
Merge tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux into soc/dt 2026-08-10T15:21:50+00:00 Arnd Bergmann arnd@arndb.de 2026-08-10T15:21:35+00:00 545ecc3577d13188ecaba57b8f4d4b7fe021842a RISC-V Devicetrees for v7.3 Sophgo: The changes of this PR are all for CV18xx serials. There are three major changes. The first is to allow DMA multiplexer setting channel number for DMA controller; the second is to add initial RISC-V support for "Duo S" board, which uses SG2000, a dual-arch SoC (RISC-V and ARM64); the third is to add support for "Duo 256M" board, another dev-board based on SG2002 SoC. Signed-off-by: Chen Wang <chen.wang@linux.dev> * tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux: riscv: dts: sophgo: Add Milk-V Duo 256M board support riscv: dts: sophgo: cv180x: Add PWR_GPIO controller dt-bindings: soc: sophgo: add Milk-V Duo 256M board riscv64: dts: sophgo: add initial Milk-V Duo S board support riscv64: dts: sophgo: add SG2000 dtsi riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
RISC-V Devicetrees for v7.3

Sophgo:

The changes of this PR are all for CV18xx serials.
There are three major changes. The first is to allow
DMA multiplexer setting channel number for DMA controller;
the second is to add initial RISC-V support for "Duo S"
board, which uses SG2000, a dual-arch SoC (RISC-V and
ARM64); the third is to add support for "Duo 256M"
board, another dev-board based on SG2002 SoC.

Signed-off-by: Chen Wang <chen.wang@linux.dev>

* tag 'riscv-sophgo-dt-for-v7.3' of https://github.com/sophgo/linux:
  riscv: dts: sophgo: Add Milk-V Duo 256M board support
  riscv: dts: sophgo: cv180x: Add PWR_GPIO controller
  dt-bindings: soc: sophgo: add Milk-V Duo 256M board
  riscv64: dts: sophgo: add initial Milk-V Duo S board support
  riscv64: dts: sophgo: add SG2000 dtsi
  riscv: dts: sophgo: cv180x: Allow the DMA multiplexer to set channel number for DMA controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux into soc/drivers 2026-08-10T08:15:56+00:00 Arnd Bergmann arnd@arndb.de 2026-08-10T08:15:48+00:00 30502a6a727fe44c784c5e21da571023a7e52a20 FSL SOC Changes for 7.3 Freescale QUICC Engine: - Use generic I/O helpers in interrupt controller for IO Ports - Move CONFIG_QE_GPIO out of powerpc - Fix DT scan for GPIO nodes - Convert IO ports interrupt controller to generic IRQ chip - Add support of IRQs in GPIO controller - Implement get_direction() in GPIO controller - Check platform_driver_register() in interrupt controller for IO Ports Data Path I/O: - Replace maintainer - Remove redundant dev_err() - Fix kernel-doc typos Freescale Management Complex: - Use strscpy() to copy strings into arrays - Remove redundant dev_err() - Drop unused assignment of acpi_device_id::driver_data Other changes: - Add kernel and device tree binding support for RCW override, completing the SerDes PHY driver functionality - Fix kernel-doc warnings and typos in DPAA header * tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux: (31 commits) bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data soc: fsl: qe: check platform_driver_register() in qe_ic_of_init() phy: lynx-10g: use RCW override procedure for dynamic protocol change soc: fsl: guts: implement the RCW override procedure dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region soc: fsl: guts: make fsl_soc_data available after fsl_guts_init() soc: fsl: guts: make it easier to determine on which SoC we are running soc: fsl: guts: add a central fsl_guts_read() function soc: fsl: guts: add a global structure to hold state soc: fsl: guts: use a macro to encode the DCFG CCSR space soc: fsl: guts: perform fsl_guts_init() error teardown in reverse order of setup soc: fsl: dpio: fix kernel-doc typos soc: fsl: fix kernel-doc warnings and typos bus: fsl-mc: Remove redundant dev_err() soc: fsl: qe: Add support of IRQs in QE GPIO soc: fsl: qe: Rename irq variable to parent_irq soc: fsl: qe: Convert to generic IRQ chip soc: fsl: qe: Handle spurious interrupts soc: fsl: qe: Iterate over all pending interrupts in cascade handler soc: fsl: qe: Use generic_handle_domain_irq() ... Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
FSL SOC Changes for 7.3

Freescale QUICC Engine:
- Use generic I/O helpers in interrupt controller for IO Ports
- Move CONFIG_QE_GPIO out of powerpc
- Fix DT scan for GPIO nodes
- Convert IO ports interrupt controller to generic IRQ chip
- Add support of IRQs in GPIO controller
- Implement get_direction() in GPIO controller
- Check platform_driver_register() in interrupt controller for IO Ports

Data Path I/O:
- Replace maintainer
- Remove redundant dev_err()
- Fix kernel-doc typos

Freescale Management Complex:
- Use strscpy() to copy strings into arrays
- Remove redundant dev_err()
- Drop unused assignment of acpi_device_id::driver_data

Other changes:
- Add kernel and device tree binding support for RCW override,
completing the SerDes PHY driver functionality
- Fix kernel-doc warnings and typos in DPAA header

* tag 'soc_fsl-7.3-1' of https://git.kernel.org/pub/scm/linux/kernel/git/chleroy/linux: (31 commits)
  bus: fsl-mc: drop unused assignment of acpi_device_id::driver_data
  soc: fsl: qe: check platform_driver_register() in qe_ic_of_init()
  phy: lynx-10g: use RCW override procedure for dynamic protocol change
  soc: fsl: guts: implement the RCW override procedure
  dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region
  soc: fsl: guts: make fsl_soc_data available after fsl_guts_init()
  soc: fsl: guts: make it easier to determine on which SoC we are running
  soc: fsl: guts: add a central fsl_guts_read() function
  soc: fsl: guts: add a global structure to hold state
  soc: fsl: guts: use a macro to encode the DCFG CCSR space
  soc: fsl: guts: perform fsl_guts_init() error teardown in reverse order of setup
  soc: fsl: dpio: fix kernel-doc typos
  soc: fsl: fix kernel-doc warnings and typos
  bus: fsl-mc: Remove redundant dev_err()
  soc: fsl: qe: Add support of IRQs in QE GPIO
  soc: fsl: qe: Rename irq variable to parent_irq
  soc: fsl: qe: Convert to generic IRQ chip
  soc: fsl: qe: Handle spurious interrupts
  soc: fsl: qe: Iterate over all pending interrupts in cascade handler
  soc: fsl: qe: Use generic_handle_domain_irq()
  ...

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux into soc/drivers 2026-08-10T08:05:44+00:00 Arnd Bergmann arnd@arndb.de 2026-08-10T08:05:42+00:00 ec833fd504d9c9063a3c2ebffbcbfb1943389572 Apple Soc driver updates for 7.3 - New driver and dt-bindings for Apple PMGR misc controls, which tweaks various global power related states and saves about 1W of power on M1 Pro/Max/Ultra during s2idle. - A small fix for device links in SART Signed-off-by: Sven Peter <sven@kernel.org> * tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux: soc: apple: Add driver for Apple PMGR misc controls dt-bindings: soc: apple: Add Apple PMGR misc controls soc: apple: sart: require device link for consumers Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
Apple Soc driver updates for 7.3

- New driver and dt-bindings for Apple PMGR misc controls, which tweaks
  various global power related states and saves about 1W of power on M1
  Pro/Max/Ultra during s2idle.
- A small fix for device links in SART

Signed-off-by: Sven Peter <sven@kernel.org>

* tag 'apple-soc-drivers-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/sven/linux:
  soc: apple: Add driver for Apple PMGR misc controls
  dt-bindings: soc: apple: Add Apple PMGR misc controls
  soc: apple: sart: require device link for consumers

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers 2026-08-10T08:00:21+00:00 Arnd Bergmann arnd@arndb.de 2026-08-10T08:00:14+00:00 93d524fb91fdd1f03e7523fb361c1ff249dc2684 More Qualcomm driver updates for v7.3 Add SMEM parsing for DDR configuration data and use its highest bank address bit to select the appropriate UBWC configuration. Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers. Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16. Correct GENI firmware-size validation using the hardware CFG RAM depth and correct the PMIC GLINK Thunderbolt extradata layout. Document the Nord AOSS side channel and the IMEM minidump SRAM property. Clean up Qualcomm statistics macros and the WCNSS binding schema. * tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux: media: qcom: Switch to generic PAS TZ APIs dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel dt-bindings: sram: qcom,imem: Add minidump-sram pattern property soc: qcom: qcom_stats: Replace CLIENT_VOTES_OFFSET macro with sizeof() soc: qcom: qcom_stats: Remove unused macro definitions soc: qcom: ubwc: Get HBB from SMEM soc: qcom: smem: Expose DDR data from SMEM soc: qcom: smem: Use 'unsigned int' instead of 'unsigned' firmware: qcom: scm: Fix tzmem state on probe retry firmware: qcom: scm: Fix reserved memory cleanup on probe failure firmware: qcom: scm: Fix NULL dereference in IRQ handler before __scm is published firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A16 (UX3607OA) soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size soc: qcom: pmic_glink_altmode: Define the TBT extradata properly dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
More Qualcomm driver updates for v7.3

Add SMEM parsing for DDR configuration data and use its highest bank
address bit to select the appropriate UBWC configuration.

Enable generic PAS trusted-zone APIs for the Iris and Venus media drivers.

Fix SCM probe retry state, reserved-memory cleanup, and an early IRQ-handler
NULL dereference. Enable QSEECOM EFI variable access on the Asus Zenbook A16.

Correct GENI firmware-size validation using the hardware CFG RAM depth and
correct the PMIC GLINK Thunderbolt extradata layout.

Document the Nord AOSS side channel and the IMEM minidump SRAM property.
Clean up Qualcomm statistics macros and the WCNSS binding schema.

* tag 'qcom-drivers-for-7.3-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  media: qcom: Switch to generic PAS TZ APIs
  dt-bindings: soc: qcom,aoss-qmp: Document Nord AOSS side channel
  dt-bindings: sram: qcom,imem: Add minidump-sram pattern property
  soc: qcom: qcom_stats: Replace CLIENT_VOTES_OFFSET macro with sizeof()
  soc: qcom: qcom_stats: Remove unused macro definitions
  soc: qcom: ubwc: Get HBB from SMEM
  soc: qcom: smem: Expose DDR data from SMEM
  soc: qcom: smem: Use 'unsigned int' instead of 'unsigned'
  firmware: qcom: scm: Fix tzmem state on probe retry
  firmware: qcom: scm: Fix reserved memory cleanup on probe failure
  firmware: qcom: scm: Fix NULL dereference in IRQ handler before __scm is published
  firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A16 (UX3607OA)
  soc: qcom: geni-se: Use HW PROG_RAM_DEPTH to validate firmware size
  soc: qcom: pmic_glink_altmode: Define the TBT extradata properly
  dt-bindings: soc: qcom,wcnss: Drop redundant $ref of firmware-name property

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Merge tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux into soc/dt 2026-08-08T16:43:27+00:00 Alexandre Belloni alexandre.belloni@bootlin.com 2026-08-08T16:43:27+00:00 b8b3f6e9747b0acfa4625f243d0f222aa8a4f53a arm64: dts: NXP device tree updates for v7.3 New boards and SOM support: - Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax (with Sonata and Symphony carrier boards) - TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx on MBa93xxCA - imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL audio, Cortex-M4F remoteproc and UART overlay i.MX8: - PCIe: add power supply properties to Root Port nodes. - imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec; - imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm fix HDMI DDC pinctrl - imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2, capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input keys, header UARTs - imx8mq-evk: add DCSS node, uart3/bluetooth node - imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes; fix LPCG clock indices for ASRC0; add Variscite Symphony board support - imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7, gpio-keys power button; correct SRAM node address/size; update rpmsg resource table address; rename 9x9-evk model string - imx8mp: enable MU2 for DSP communication (imx8mp-ab2) i.MX9: - PCIe: add Root Port nodes with correct outbound address space for imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe; remove 'supports-clkreq' from imx943-evk PCIe1 - imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi); enable NETC block control and in-band SFP status (imx95-var-dart); add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc) - imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards; update TMU compatible string; fix memory node for imx93-kontron - imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB range; USB phy adjustments (imx91-tqma9131) Layerscape / S32G: - ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi files; transition to device-specific SerDes compatible strings - s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl Cleanup and warning fixes: - correct imx8/s32g3 indentation - imx8mp: add missing #sound-dai-cells to xcvr * tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (131 commits) arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe arm64: dts: imx94-xspi: add the DMA channels arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP arm64: dts: imx8ulp-evk: Update rpmsg resource table address arm64: dts: imx943-evk: Add CM7 and CM33S nodes arm64: dts: imx952-evk: Add CM7 node and related memory nodes arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes arm64: dts: imx8qm-var-som-symphony: enable expansion header UART arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET arm64: dts: imx8ulp-evk: Enable LPUART7 arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth arm64: dts: imx8ulp-evk: Add gpio-keys node for power button ... Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
arm64: dts: NXP device tree updates for v7.3

New boards and SOM support:
- Variscite DART-MX8M-MINI, DART-MX8M-PLUS, VAR-SOM-MX8 QuadMax
  (with Sonata and Symphony carrier boards)
- TQMa8MPxS (i.MX8MP) with LVDS overlays, TQMa9596LA on MBa95xxCA; TQMa91xx
  on MBa93xxCA
- imx8mm-verdin: Toradex DSI displays (7"/10.1"), HDMI adapter, NAU8822 BTL
  audio, Cortex-M4F remoteproc and UART overlay

i.MX8:
- PCIe: add power supply properties to Root Port nodes.
- imx8mp-evk add typec and usb3_phy1 tuning; imx8mq-evk add typec;
- imx8mp-evk add flexcan2 overlay and CAN2/MICFIL board mux; imx8mp-frdm
  fix HDMI DDC pinctrl
- imx8mp-var-som-symphony: add second Ethernet, CAN, PWM1, ECSPI2,
  capacitive touchscreen, HDMI, PCIe, USB, TPM, external RTC, input
  keys, header UARTs
- imx8mq-evk: add DCSS node, uart3/bluetooth node
- imx8qm: add SCU power key, lsio mu8/mu8b, spdif1, lpuart4 nodes;
  fix LPCG clock indices for ASRC0; add Variscite Symphony board support
- imx8ulp: add I3C2, eDMA channel properties, LPUART6 (BT) and LPUART7,
  gpio-keys power button; correct SRAM node address/size; update rpmsg
  resource table address; rename 9x9-evk model string
- imx8mp: enable MU2 for DSP communication (imx8mp-ab2)

i.MX9:
- PCIe: add Root Port nodes with correct outbound address space for
  imx94/imx943/imx95; add dma/intr/aer/pme interrupts for imx95 PCIe;
  remove 'supports-clkreq' from imx943-evk PCIe1
- imx95: switch USB3 controller to flattened model; add CM7/CM33S nodes
  for imx943/imx952/imx95-19x19-evk; add imx94 DMA channels (xspi);
  enable NETC block control and in-band SFP status (imx95-var-dart);
  add wm8904 DMICDAT1; add lpuart5 alias (imx95-toradex-smarc)
- imx93: add LVDS Display Bridge support with DY1212W-4856 panel overlay
  for imx93-11x11-evk; add LVDS overlays for imx93-tqma9352 boards;
  update TMU compatible string; fix memory node for imx93-kontron
- imx91: add WM8524 and PDM microphone sound cards, CAN overlay, audio
  board muxes (imx91-9x9-qsb); move ELE reserved memory into 512MB
  range; USB phy adjustments (imx91-tqma9131)

Layerscape / S32G:
- ls1028a/ls1046a/ls1088a/ls208xa/lx2160a/lx2162a: describe Lynx 10G
  SerDes blocks; refactor lx2160a PCIe and SerDes into separate dtsi
  files; transition to device-specific SerDes compatible strings
- s32g: add GPR syscon region; describe GPIO and EIRQ in SIUL2 pinctrl

Cleanup and warning fixes:
- correct imx8/s32g3 indentation
- imx8mp: add missing #sound-dai-cells to xcvr

* tag 'imx-dt64-7.3' of https://git.kernel.org/pub/scm/linux/kernel/git/frank.li/linux: (131 commits)
  arm64: dts: imx95: Add dma, intr, aer and pme interrupts for PCIe
  arm64: dts: imx94-xspi: add the DMA channels
  arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F UART_4 overlay
  arm64: dts: freescale: imx8mm-verdin: Add Cortex-M4F remoteproc
  arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 7" DSI
  arm64: dts: freescale: imx8mm-verdin: Add Toradex Capacitive Touch Display 10.1" DSI
  arm64: dts: freescale: imx8mm-verdin: Add Toradex DSI to LVDS adapter with 10.1" display
  arm64: dts: freescale: imx8mm-verdin: Add DSI to HDMI adapter overlay
  arm64: dts: freescale: imx8mm-verdin: Add NAU8822 Bridge Tied Load
  arm64: dts: imx95-var-dart-sonata: enable in-band status for SFP
  arm64: dts: imx8ulp-evk: Update rpmsg resource table address
  arm64: dts: imx943-evk: Add CM7 and CM33S nodes
  arm64: dts: imx952-evk: Add CM7 node and related memory nodes
  arm64: dts: imx95-19x19-evk: Add CM7 node and related memory nodes
  arm64: dts: imx8qm-var-som-symphony: enable expansion header UART
  arm64: dts: imx8ulp-9x9-evk: Rename model string to reflect die size
  arm64: dts: imx8ulp-evk: Change the values of some PCRs of ENET
  arm64: dts: imx8ulp-evk: Enable LPUART7
  arm64: dts: imx8ulp-evk: Enable LPUART6 for Bluetooth
  arm64: dts: imx8ulp-evk: Add gpio-keys node for power button
  ...

Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: fsl: layerscape-dcfg: define DCFG_DCSR region 2026-08-07T04:54:23+00:00 Vladimir Oltean vladimir.oltean@nxp.com 2026-07-21T23:16:01+00:00 d1b710f463fc26081d37c56a85b15dfa25560e36 In Layerscape (Arm) and QorIQ (PowerPC) devices, hardware peripherals are accessed by the CPU through a portion of the SoC address space called CCSR ("Configuration, Control, and Status Registers"). All hardware IP blocks have their registers mapped here, and the Device Configuration block makes no exception. However, there exists a secondary range of the address space named DCSR ("Debug Control and Status Registers") which, like CCSR, also holds registers of hardware IP blocks, except the DCSR contents is hidden in all public reference manuals. The intention of the CCSR/DCSR split, to the best of my knowledge, was to place the functionality that is too low level for normal use, and which is necessary only for debug, in a completely separate address space which can be hidden. A use case has appeared where networking SerDes lanes need to be reconfigured at runtime for a different protocol (example: 10GBase-R to SGMII), and the architecture of the SoCs does not normally permit that. The Reset Configuration Word (RCW) is a data structure read by the SoC preboot loader (PBL) which contains stuff like pinmuxing and SerDes protocol mapping for each lane. The RCW that the PBL has loaded is visible in the DCFG block's normal status registers (from CCSR), as read only. Turns out, the RCW is also mapped in the DCFG's shadow register map (in DCSR), in a write-only form. Writing to the RCW registers from the DCFG's DCSR space to change what the PBL has loaded is called "RCW override". It has been validated that the RCW override procedure is necessary to reconfigure the networking data path when a SerDes lane performs a major protocol change. It changes some internal muxes which connect the PCS to either the 10G MAC or to the 1G MAC. Defining the DCSR area of the DCFG as a secondary 'reg' array element allows operating systems to perform RCW overrides. Since it is introduced late in the binding's lifetime, it is optional. It can be identified by name, but also by index (first 'reg' is CCSR). Note that while all SoCs should have a DCFG register block in DCSR, we only need to expose it for the SoCs where the RCW override procedure is known to be needed and has been validated. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20260721231603.67865-8-vladimir.oltean@nxp.com Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org> 
In Layerscape (Arm) and QorIQ (PowerPC) devices, hardware peripherals
are accessed by the CPU through a portion of the SoC address space
called CCSR ("Configuration, Control, and Status Registers"). All
hardware IP blocks have their registers mapped here, and the Device
Configuration block makes no exception.

However, there exists a secondary range of the address space named DCSR
("Debug Control and Status Registers") which, like CCSR, also holds
registers of hardware IP blocks, except the DCSR contents is hidden in
all public reference manuals.

The intention of the CCSR/DCSR split, to the best of my knowledge, was
to place the functionality that is too low level for normal use, and
which is necessary only for debug, in a completely separate address
space which can be hidden.

A use case has appeared where networking SerDes lanes need to be
reconfigured at runtime for a different protocol (example: 10GBase-R to
SGMII), and the architecture of the SoCs does not normally permit that.
The Reset Configuration Word (RCW) is a data structure read by the SoC
preboot loader (PBL) which contains stuff like pinmuxing and SerDes
protocol mapping for each lane.

The RCW that the PBL has loaded is visible in the DCFG block's normal
status registers (from CCSR), as read only. Turns out, the RCW is also
mapped in the DCFG's shadow register map (in DCSR), in a write-only
form. Writing to the RCW registers from the DCFG's DCSR space to change
what the PBL has loaded is called "RCW override".

It has been validated that the RCW override procedure is necessary to
reconfigure the networking data path when a SerDes lane performs a major
protocol change. It changes some internal muxes which connect the PCS to
either the 10G MAC or to the 1G MAC.

Defining the DCSR area of the DCFG as a secondary 'reg' array element
allows operating systems to perform RCW overrides. Since it is
introduced late in the binding's lifetime, it is optional. It can be
identified by name, but also by index (first 'reg' is CCSR).

Note that while all SoCs should have a DCFG register block in DCSR, we
only need to expose it for the SoCs where the RCW override procedure is
known to be needed and has been validated.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20260721231603.67865-8-vladimir.oltean@nxp.com
Signed-off-by: Christophe Leroy (CS GROUP) <chleroy@kernel.org>