linux.git/Documentation/devicetree/bindings/serial, branch v4.16

Merge tag 'devicetree-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux

2018-02-01T18:57:45+00:00

Pull DeviceTree updates from Rob Herring:

 - Convert to use memblock_virt_alloc in DT code which supports
   bootmem arches. With this we can remove the arch specific
   early_init_dt_alloc_memory_arch() functions.

 - Enable running the DT unittests on UML

 - Use SPDX license tags on DT files

 - Fix early FDT kconfig ifdef logic

 - Clean-up unittest Makefile

 - Fix function comment for of_irq_parse_raw

 - Add missing documentation for linux,initrd-{start,end} properties

 - Clean-up of binding examples using uppercase hex

 - Add trivial devices W83773G and Infineon TLV493D-A1B6

 - Add missing STM32 SoC bindings

 - Various small binding doc fixes

* tag 'devicetree-for-4.16' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (23 commits)
  xtensa: remove arch specific early DT functions
  x86: remove arch specific early_init_dt_alloc_memory_arch
  nios2: remove arch specific early_init_dt_alloc_memory_arch
  mips: remove arch specific early_init_dt_alloc_memory_arch
  metag: remove arch specific early DT functions
  cris: remove arch specific early DT functions
  libfdt: remove unnecessary include directive from 
  of: unittest: refactor Makefile
  of/fdt: use memblock_virt_alloc for early alloc
  of: Use SPDX license tag for DT files
  of/fdt: Fix #ifdef dependency of early flattree declarations
  dt-bindings: h8300 clocksource: correct spelling of pulse
  dt-bindings: imx6q-pcie: Add required property for i.MX6SX
  mmc: Don't reference Linux-specific OF_GPIO_ACTIVE_LOW flag in DT binding
  dt-bindings: Use lower case hex in unit-addresses
  dt-bindings: display: panel: Fix compatible string for Toshiba LT089AC29000
  dt-bindings: Add Infineon TLV493D-A1B6
  dt-bindings: mailbox: ti,message-manager: Fix interrupt name error
  dt-bindings: chosen: Document linux,initrd-{start,end}
  dt-bindings: arm: document supported STM32 SoC family
  ...

serial: 8250_ingenic: Add support for the JZ4770 SoC

2018-01-09T15:49:14+00:00

The JZ4770 SoC's UART is no different from the other JZ SoCs, so this
commit simply adds the ingenic,jz4770-uart compatible string.

Signed-off-by: Paul Cercueil 
Acked-by: Rob Herring 
Signed-off-by: Greg Kroah-Hartman

dt-bindings: Use lower case hex in unit-addresses

2017-12-26T16:37:05+00:00

DT unit addresses should be lower case hex. Fix all the
binding examples.

Converted with the following command from Krzysztof Kozlowski:

sed -e 's/@\([a-fA-F0-9_-]*\) {/@\L\1 {/' -i $(find Documentation/devicetree/bindings -name '*.txt')

Signed-off-by: Rob Herring

serial: max310x: Document clock setup

2017-12-19T08:59:02+00:00

As a kernel newcomer, I got bitten by lack of examples on this front. I
had troubles figuring out where these clocks could be defined ("/clocks"
is where the generic infrastructure expects them).

One should also ensure that a unique name is used. Generic names such as
"osc" tend to be already used by some board-wide clock crystals.

Signed-off-by: Jan Kundrát 
Signed-off-by: Greg Kroah-Hartman

serial: max310x: Use level-triggered interrupts

2017-12-19T08:59:01+00:00

I was getting this trace along with a disabled IRQ when I was generating
heavy traffic over four daisy-chained UARTs (MAX14830) on my test kit
(Marvell Armada AM388, Solidrun Clearfog Base):

    irq 51: nobody cared (try booting with the "irqpoll" option)
    CPU: 0 PID: 68 Comm: irq/51-spi1.2 Not tainted 4.14.4 #7
    Hardware name: Marvell Armada 380/385 (Device Tree)
    [] (unwind_backtrace) from [] (show_stack+0x10/0x14)
    [] (show_stack) from [] (dump_stack+0x84/0x98)
    [] (dump_stack) from [] (__report_bad_irq+0x28/0xcc)
    [] (__report_bad_irq) from [] (note_interrupt+0x28c/0x2dc)
    [] (note_interrupt) from [] (handle_irq_event_percpu+0x4c/0x58)
    [] (handle_irq_event_percpu) from [] (handle_irq_event+0x44/0x68)
    [] (handle_irq_event) from [] (handle_edge_irq+0x12c/0x1dc)
    [] (handle_edge_irq) from [] (generic_handle_irq+0x24/0x34)
    [] (generic_handle_irq) from [] (mvebu_gpio_irq_handler+0xe0/0x184)
    [] (mvebu_gpio_irq_handler) from [] (generic_handle_irq+0x24/0x34)
    [] (generic_handle_irq) from [] (__handle_domain_irq+0x5c/0xb4)
    [] (__handle_domain_irq) from [] (gic_handle_irq+0x4c/0x90)
    [] (gic_handle_irq) from [] (__irq_svc+0x6c/0x90)
    Exception stack(0xeea77c30 to 0xeea77c78)
    7c20:                                     0000000a 018cba80 0000000a f098f680
    7c40: 0000020a f098f680 00000008 0000020a 018cba80 00000001 ee9302a0 eea76000
    7c60: ef2b2640 eea77c80 c050687c c0506894 80070013 ffffffff
    [] (__irq_svc) from [] (orion_spi_setup_transfer+0x118/0x20c)
    [] (orion_spi_setup_transfer) from [] (orion_spi_transfer_one+0x1c/0x26c)
    [] (orion_spi_transfer_one) from [] (spi_transfer_one_message+0xec/0x500)
    [] (spi_transfer_one_message) from [] (__spi_pump_messages+0x3f4/0x680)
    [] (__spi_pump_messages) from [] (__spi_sync+0x1fc/0x200)
    [] (__spi_sync) from [] (spi_sync+0x24/0x3c)
    [] (spi_sync) from [] (spi_write_then_read+0xd0/0x17c)
    [] (spi_write_then_read) from [] (_regmap_raw_read+0xb0/0x250)
    [] (_regmap_raw_read) from [] (_regmap_bus_read+0x24/0x4c)
    [] (_regmap_bus_read) from [] (_regmap_read+0x60/0x148)
    [] (_regmap_read) from [] (regmap_read+0x3c/0x5c)
    [] (regmap_read) from [] (max310x_port_irq+0x104/0x2dc)
    [] (max310x_port_irq) from [] (max310x_ist+0x68/0xc0)
    [] (max310x_ist) from [] (irq_thread_fn+0x1c/0x54)
    [] (irq_thread_fn) from [] (irq_thread+0x12c/0x1f0)
    [] (irq_thread) from [] (kthread+0x128/0x158)
    [] (kthread) from [] (ret_from_fork+0x14/0x24)
    handlers:
    [] irq_default_primary_handler threaded [] max310x_ist
    Disabling IRQ #51

On a multi-UART max310x, each UART has its own interrupt status register
which automatically de-asserts the IRQ line upon read. (There are also
top-level IRQ indicator registers which are not clear-on-read, but they
are not relevant here.) It was quite possible to receive a pending IRQ
for, e.g., UART0, enter the threaded IRQ handler, clear the ISR for
UART0 which de-asserts the IRQ line, and then race with another event on
the same chip, but a different UART channel. That resulted in another
edge on the shared-within-the-chip IRQ line which got intercepted by the
kernel.

That all led to an edge-level interrupt which was not being handled by
anybody because our threaded handler hasn't finished yet. As the chip
actually uses *level* triggered IRQs, let's convert the example DT
bindings to these.

Signed-off-by: Jan Kundrát 
Signed-off-by: Greg Kroah-Hartman

dt-bindings: mvebu-uart: update documentation with extended UART

2017-12-15T19:27:44+00:00

Update the device tree binding documentation for the Marvell EBU UART,
in order to allow describing the extended UART IP block, in addition to
the already supported standard UART IP. This requires adding a new
compatible string, the introduction of a clocks property, and extensions
to the interrupts property.

Signed-off-by: Miquel Raynal 
Reviewed-by: Gregory CLEMENT 
Acked-by: Rob Herring 
Signed-off-by: Greg Kroah-Hartman

Merge 4.15-rc3 into tty-next

2017-12-11T07:41:08+00:00

We want the serial/tty fixes in here as well.

Signed-off-by: Greg Kroah-Hartman

dt-bindings: Remove leading 0x from bindings notation

2017-12-06T20:56:33+00:00

Improve the binding example by removing all the leading 0x to fix the
following dtc warnings:

Warning (unit_address_format): Node /XXX unit name should not have leading "0x"

Converted using the following command:

find Documentation/devicetree/bindings -name "*.txt" -exec sed -i -e 's/([^ ])\@0x([0-9a-f])/$1\@$2/g' {} +

This is a follow up to commit 48c926cd3414

Signed-off-by: Mathieu Malaterre 
Signed-off-by: Rob Herring

dt-bindings: serial: Add common rs485 binding for RTS polarity

2017-11-28T15:04:57+00:00

rs485 allows for robust half-duplex serial communication.  It is often
implemented by attaching an rs485 transceiver to a UART.  The UART's
RTS line is wired to the transceiver's Transmit Enable pin and
determines whether the transceiver is sending or receiving.

Examples for such transceivers are Maxim MAX13451E and TI SN65HVD1781A:
https://datasheets.maximintegrated.com/en/ds/MAX13450E-MAX13451E.pdf
http://www.ti.com/lit/ds/symlink/sn65hvd1781a-q1.pdf

In the devicetree, the transceiver itself is not represented, only the
UART is.  A few rs485-specific dt-bindings already exist and these go
into the UART's device node.

This commit adds a binding to set the RTS polarity.  Most (if not all)
transceivers require the Transmit Enable pin be driven high for sending,
but in some cases boards may negate the pin and RTS must then be driven
low.  Consequently the polarity defaults to active high but can be
inverted with the newly added "rs485-rts-active-low" binding.

Document this binding in rs485.txt and in the two drivers fsl-imx-uart
and fsl-lpuart that are about to be amended with support for it.

Curiously, the omap_serial driver defaults to active low and already
supports an "rs485-rts-active-high" binding to invert the polarity.
This is left unchanged to retain compatibility, but the binding is
herewith documented.

Cc: Mark Jackson 
Cc: Michał Oleszczyk 
Cc: Rafael Gago Castano 
Cc: Sascha Hauer 
Acked-by: Rob Herring 
Signed-off-by: Lukas Wunner 
Acked-by: Uwe Kleine-König 
Signed-off-by: Greg Kroah-Hartman

dt-bindings: serial: fsl-imx-uart: Remove 'fsl,irda-mode' property

2017-11-28T14:32:32+00:00

'fsl,irda-mode' property has been removed since commit afe9cbb1a6ad
("serial: imx: drop support for IRDA"), so remove it from the binding
document.

Signed-off-by: Fabio Estevam 
Acked-by: Rob Herring 
Signed-off-by: Greg Kroah-Hartman