linux.git/Documentation/devicetree/bindings/reset, branch v6.15 Linux kernel source tree dt-bindings: xilinx: Remove myself from maintainership 2025-04-07T14:34:35+00:00 Mubin Sayyed mubin.sayyed@amd.com 2025-04-03T06:08:36+00:00 1296dcbad2316882f98559762b518eaa6aefcd92 As I am leaving AMD and will no longer be maintaining these platform drivers, so removing myself from maintainership. Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com> Acked-by: Damien Le Moal <dlemoal@kernel.org> Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Link: https://lore.kernel.org/r/20250403060836.2602361-1-mubin.sayyed@amd.com Signed-off-by: Rob Herring (Arm) <robh@kernel.org> 
As I am leaving AMD and will no longer be maintaining
these platform drivers, so removing myself from maintainership.

Signed-off-by: Mubin Sayyed <mubin.sayyed@amd.com>
Acked-by: Damien Le Moal <dlemoal@kernel.org>
Acked-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org>
Link: https://lore.kernel.org/r/20250403060836.2602361-1-mubin.sayyed@amd.com
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
dt-bindings: reset: atmel,at91sam9260-reset: add sam9x7 2025-03-13T08:01:15+00:00 Varshini Rajendran varshini.rajendran@microchip.com 2024-10-10T12:04:19+00:00 d41f0d0bbd79a40a298582c5a3a06ce580e0db96 Add documentation for SAM9X7 reset controller. Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Acked-by: Philipp Zabel <p.zabel@pengutronix.de> Acked-by: Dharma Balasubiramani <dharma.b@microchip.com> Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org> Link: https://lore.kernel.org/r/20241010120419.93043-1-varshini.rajendran@microchip.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add documentation for SAM9X7 reset controller.

Signed-off-by: Varshini Rajendran <varshini.rajendran@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Philipp Zabel <p.zabel@pengutronix.de>
Acked-by: Dharma Balasubiramani <dharma.b@microchip.com>
Reviewed-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Link: https://lore.kernel.org/r/20241010120419.93043-1-varshini.rajendran@microchip.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
dt-bindings: clock: convert stm32 rcc bindings to json-schema 2025-01-15T23:17:05+00:00 Dario Binacchi dario.binacchi@amarulasolutions.com 2025-01-14T18:19:46+00:00 ebca39700f343c42fe37d9606980e8591801c46f The patch converts st,stm32-rcc.txt to the JSON schema, but it does more than that. The old bindings, in fact, only covered the stm32f{4,7} platforms and not the stm32h7. Therefore, to avoid patch submission tests failing, it was necessary to add the corresponding compatible (i. e. st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead of the 2 required for the stm32f{4,7} platforms. Additionally, the old bindings made no mention of the st,syscfg property, which is used by both the stm32f{4,7} and the stm32h7 platforms. The patch also fixes the files referencing to the old st,stm32-rcc.txt. Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
The patch converts st,stm32-rcc.txt to the JSON schema, but it does more
than that. The old bindings, in fact, only covered the stm32f{4,7}
platforms and not the stm32h7. Therefore, to avoid patch submission tests
failing, it was necessary to add the corresponding compatible (i. e.
st,stm32h743-rcc) and specify that, in this case, 3 are the clocks instead
of the 2 required for the stm32f{4,7} platforms.
Additionally, the old bindings made no mention of the st,syscfg property,
which is used by both the stm32f{4,7} and the stm32h7 platforms.

The patch also fixes the files referencing to the old st,stm32-rcc.txt.

Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Link: https://lore.kernel.org/r/20250114182021.670435-2-dario.binacchi@amarulasolutions.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: reset: npcm: add clock properties 2024-10-17T22:17:51+00:00 Tomer Maimon tmaimon77@gmail.com 2024-09-12T19:10:36+00:00 d62f45b5e95fa9e557af071915a3fbfa0d766c8f This commit adds a 25MHz reference clock and clock-cell properties to the NPCM reset document. The addition is necessitated by the integration of the NPCM8xx clock auxiliary bus device into the NPCM reset driver. The inclusion of the NPCM8xx clock properties in the reset document is crucial as the reset block also serves as a clock provider for the NPCM8xx clock. This enhancement is intended to facilitate the use of the NPCM8xx clock driver. Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20240912191038.981105-2-tmaimon77@gmail.com Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
This commit adds a 25MHz reference clock and clock-cell properties to
the NPCM reset document. The addition is necessitated by the integration
of the NPCM8xx clock auxiliary bus device into the NPCM reset driver.

The inclusion of the NPCM8xx clock properties in the reset document is
crucial as the reset block also serves as a clock provider for the
NPCM8xx clock. This enhancement is intended to facilitate the use of the
NPCM8xx clock driver.

Signed-off-by: Tomer Maimon <tmaimon77@gmail.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20240912191038.981105-2-tmaimon77@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Merge tag 'soc-drivers-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2024-09-17T08:48:09+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-09-17T08:48:09+00:00 b8979c6b4d0d1b36e94f5bc483fd86e38107e554 Pull SoC driver updates from Arnd Bergmann: "The driver updates seem larger this time around, with changes is many of the SoC specific drivers, both the custom drivers/soc ones and the closely related subsystems (memory, bus, firmware, reset, ...). The at91 platform gains support for sam9x7 chips in the soc and power management code. This is the latest variant of one of the oldest still supported SoC families, using the ARM9 (ARMv5) core. As usual, the qualcomm snapdragon platform gets a ton of updates in many of their drivers to add more features and additional SoC support. Most of these are somewhat firmware related as the platform has a number of firmware based interfaces to the kernel. A notable addition here is the inclusion of trace events to two of these drivers. Herve Codina and Christophe Leroy are now sending updates for drivers/soc/fsl/ code through the SoC tree, this contains both PowerPC and Arm specific platforms and has previously been problematic to maintain. The first update here contains support for newer PowerPC variants and some cleanups. The turris mox firmware driver has a number of updates, mostly cleanups. The Arm SCMI firmware driver gets a major rework to modularize the existing code into separately loadable drivers for the various transports, the addition of custom NXP i.MX9 interfaces and a number of smaller updates. The Arm FF-A firmware driver gets a feature update to support the v1.2 version of the specification. The reset controller drivers have some smaller cleanups and a newly added driver for the Intel/Mobileye EyeQ5/EyeQ6 MIPS SoCs. The memory controller drivers get some cleanups and refactoring for Tegra, TI, Freescale/NXP and a couple more platforms. Finally there are lots of minor updates to firmware (raspberry pi, tegra, imx), bus (sunxi, omap, tegra) and soc (rockchips, tegra, amlogic, mediatek) drivers and their DT bindings" * tag 'soc-drivers-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (212 commits) firmware: imx: remove duplicate scmi_imx_misc_ctrl_get() platform: cznic: turris-omnia-mcu: Fix error check in omnia_mcu_register_trng() bus: sunxi-rsb: Simplify code with dev_err_probe() soc: fsl: qe: ucc: Export ucc_mux_set_grant_tsa_bkpt soc: fsl: cpm1: qmc: Fix dependency on fsl_soc.h dt-bindings: arm: rockchip: Add rk3576 compatible string to pmu.yaml soc: fsl: qbman: Remove redundant warnings soc: fsl: qbman: Use iommu_paging_domain_alloc() MAINTAINERS: Add QE files related to the Freescale QMC controller soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation soc: fsl: qe: Add missing PUSHSCHED command soc: fsl: qe: Add resource-managed muram allocators soc: fsl: cpm1: qmc: Introduce qmc_version soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC soc: fsl: cpm1: qmc: Handle RPACK initialization soc: fsl: cpm1: qmc: Rename qmc_chan_command() soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version soc: fsl: cpm1: qmc: Re-order probe() operations ... 
Pull SoC driver updates from Arnd Bergmann:
 "The driver updates seem larger this time around, with changes is many
  of the SoC specific drivers, both the custom drivers/soc ones and the
  closely related subsystems (memory, bus, firmware, reset, ...).

  The at91 platform gains support for sam9x7 chips in the soc and power
  management code. This is the latest variant of one of the oldest still
  supported SoC families, using the ARM9 (ARMv5) core.

  As usual, the qualcomm snapdragon platform gets a ton of updates in
  many of their drivers to add more features and additional SoC support.
  Most of these are somewhat firmware related as the platform has a
  number of firmware based interfaces to the kernel. A notable addition
  here is the inclusion of trace events to two of these drivers.

  Herve Codina and Christophe Leroy are now sending updates for
  drivers/soc/fsl/ code through the SoC tree, this contains both PowerPC
  and Arm specific platforms and has previously been problematic to
  maintain. The first update here contains support for newer PowerPC
  variants and some cleanups.

  The turris mox firmware driver has a number of updates, mostly
  cleanups.

  The Arm SCMI firmware driver gets a major rework to modularize the
  existing code into separately loadable drivers for the various
  transports, the addition of custom NXP i.MX9 interfaces and a number
  of smaller updates.

  The Arm FF-A firmware driver gets a feature update to support the v1.2
  version of the specification.

  The reset controller drivers have some smaller cleanups and a newly
  added driver for the Intel/Mobileye EyeQ5/EyeQ6 MIPS SoCs.

  The memory controller drivers get some cleanups and refactoring for
  Tegra, TI, Freescale/NXP and a couple more platforms.

  Finally there are lots of minor updates to firmware (raspberry pi,
  tegra, imx), bus (sunxi, omap, tegra) and soc (rockchips, tegra,
  amlogic, mediatek) drivers and their DT bindings"

* tag 'soc-drivers-6.12' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (212 commits)
  firmware: imx: remove duplicate scmi_imx_misc_ctrl_get()
  platform: cznic: turris-omnia-mcu: Fix error check in omnia_mcu_register_trng()
  bus: sunxi-rsb: Simplify code with dev_err_probe()
  soc: fsl: qe: ucc: Export ucc_mux_set_grant_tsa_bkpt
  soc: fsl: cpm1: qmc: Fix dependency on fsl_soc.h
  dt-bindings: arm: rockchip: Add rk3576 compatible string to pmu.yaml
  soc: fsl: qbman: Remove redundant warnings
  soc: fsl: qbman: Use iommu_paging_domain_alloc()
  MAINTAINERS: Add QE files related to the Freescale QMC controller
  soc: fsl: cpm1: qmc: Handle QUICC Engine (QE) soft-qmc firmware
  soc: fsl: cpm1: qmc: Add support for QUICC Engine (QE) implementation
  soc: fsl: qe: Add missing PUSHSCHED command
  soc: fsl: qe: Add resource-managed muram allocators
  soc: fsl: cpm1: qmc: Introduce qmc_version
  soc: fsl: cpm1: qmc: Rename SCC_GSMRL_MODE_QMC
  soc: fsl: cpm1: qmc: Handle RPACK initialization
  soc: fsl: cpm1: qmc: Rename qmc_chan_command()
  soc: fsl: cpm1: qmc: Introduce qmc_{init,exit}_xcc() and their CPM1 version
  soc: fsl: cpm1: qmc: Introduce qmc_init_resource() and its CPM1 version
  soc: fsl: cpm1: qmc: Re-order probe() operations
  ...
Revert "dt-bindings: reset: mobileye,eyeq5-reset: add bindings" 2024-09-02T10:12:05+00:00 Théo Lebrun theo.lebrun@bootlin.com 2024-07-30T16:06:22+00:00 ce50a775bd2ef31846df201804d920bbfc99c93f Switch from one sub-node per functionality in the system-controller to a single node representing the entire OLB instance. This is the recommended approach for controllers handling many different functionalities; it is a single controller and should be represented by a single devicetree node. The reset bindings is removed and all properties will be described by: soc/mobileye/mobileye,eyeq5-olb.yaml Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Link: https://lore.kernel.org/r/20240730-mbly-reset-v2-1-00b870a6a2ff@bootlin.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Switch from one sub-node per functionality in the system-controller to a
single node representing the entire OLB instance. This is the
recommended approach for controllers handling many different
functionalities; it is a single controller and should be represented by
a single devicetree node.

The reset bindings is removed and all properties will be described by:
soc/mobileye/mobileye,eyeq5-olb.yaml

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20240730-mbly-reset-v2-1-00b870a6a2ff@bootlin.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
dt-bindings: reset: Add Amlogic T7 reset controller 2024-09-02T10:09:17+00:00 Zelong Dong zelong.dong@amlogic.com 2024-04-22T11:11:43+00:00 47c270a9bf2188c3797e9791e2d59c411f7c9549 Add a new compatible for Amlogic T7 reset controller. Signed-off-by: Zelong Dong <zelong.dong@amlogic.com> Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20240422-t7-reset-v2-1-cb82271d3296@amlogic.com Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add a new compatible for Amlogic T7 reset controller.

Signed-off-by: Zelong Dong <zelong.dong@amlogic.com>
Signed-off-by: Kelvin Zhang <kelvin.zhang@amlogic.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240422-t7-reset-v2-1-cb82271d3296@amlogic.com
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
dt-bindings: reset: socionext,uniphier-glue-reset: add top-level constraints 2024-09-02T09:29:35+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2024-08-18T17:28:19+00:00 6bbc0fa234a2ec144a469bd35d8f68e21e69af5a Properties with variable number of items per each device are expected to have widest constraints in top-level "properties:" block and further customized (narrowed) in "if:then:". Add missing top-level constraints for clock-names and reset-names. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240818172819.121697-1-krzysztof.kozlowski@linaro.org Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:".  Add missing top-level constraints
for clock-names and reset-names.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240818172819.121697-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
dt-bindings: reset: renesas: Document RZ/G2M v3.0 (r8a774a3) reset module 2024-07-30T08:50:47+00:00 Oliver Rhodes oliver.rhodes.aj@renesas.com 2024-07-25T10:05:32+00:00 9f766e8f5c2366d7237735a826084569b5705cf4 Document bindings for the Renesas RZ/G2M v3.0 (a.k.a r8a774a3) reset module. Signed-off-by: Oliver Rhodes <oliver.rhodes.aj@renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20240725100534.5374-5-oliver.rhodes.aj@renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 
Document bindings for the Renesas RZ/G2M v3.0 (a.k.a r8a774a3) reset
module.

Signed-off-by: Oliver Rhodes <oliver.rhodes.aj@renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/20240725100534.5374-5-oliver.rhodes.aj@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Merge tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl 2024-07-21T17:25:59+00:00 Linus Torvalds torvalds@linux-foundation.org 2024-07-21T17:25:59+00:00 8e313211f7d46d42b6aa7601b972fe89dcc4a076 Pull pin control updates from Linus Walleij: "Some new drivers is the main part, the rest is cleanups and nonurgent fixes. Nothing much special about this, no core changes this time. New drivers: - Renesas RZ/V2H(P) SoC - NXP Freescale i.MX91 SoC - Nuvoton MA35D1 SoC - Qualcomm PMC8380, SM4250, SM4250 LPI Enhancements: - A slew of scoped-based simplifications of of_node_put()" * tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits) pinctrl: renesas: rzg2l: Support output enable on RZ/G2L pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions pinctrl: renesas: rzg2l: Clarify OEN read/write support dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties pinctrl: freescale: Use scope based of_node_put() cleanups pinctrl: equilibrium: Use scope based of_node_put() cleanups pinctrl: ti: iodelay: Use scope based of_node_put() cleanups pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32 pinctrl: cy8c95x0: Update cache modification pinctrl: cy8c95x0: Use cleanup.h pinctrl: renesas: r8a779h0: Remove unneeded separators pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function pinctrl: renesas: r8a779g0: Remove unneeded separators pinctrl: renesas: r8a779h0: Add AVB MII pins and groups pinctrl: renesas: r8a779g0: Fix TPU suffixes pinctrl: renesas: r8a779g0: Fix TCLK suffixes pinctrl: renesas: r8a779g0: FIX PWM suffixes pinctrl: renesas: r8a779g0: Fix IRQ suffixes ... 
Pull pin control updates from Linus Walleij:
 "Some new drivers is the main part, the rest is cleanups and nonurgent
  fixes.

  Nothing much special about this, no core changes this time.

  New drivers:

   - Renesas RZ/V2H(P) SoC

   - NXP Freescale i.MX91 SoC

   - Nuvoton MA35D1 SoC

   - Qualcomm PMC8380, SM4250, SM4250 LPI

  Enhancements:

   - A slew of scoped-based simplifications of of_node_put()"

* tag 'pinctrl-v6.11-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (110 commits)
  pinctrl: renesas: rzg2l: Support output enable on RZ/G2L
  pinctrl: renesas: rzg2l: Clean up and refactor OEN read/write functions
  pinctrl: renesas: rzg2l: Clarify OEN read/write support
  dt-bindings: pinctrl: pinctrl-single: Fix pinctrl-single,gpio-range description
  dt-bindings: pinctrl: npcm8xx: add missing pin group and mux function
  dt-bindings: pinctrl: pinctrl-single: fix schmitt related properties
  pinctrl: freescale: Use scope based of_node_put() cleanups
  pinctrl: equilibrium: Use scope based of_node_put() cleanups
  pinctrl: ti: iodelay: Use scope based of_node_put() cleanups
  pinctrl: qcom: lpass-lpi: increase MAX_NR_GPIO to 32
  pinctrl: cy8c95x0: Update cache modification
  pinctrl: cy8c95x0: Use cleanup.h
  pinctrl: renesas: r8a779h0: Remove unneeded separators
  pinctrl: renesas: r8a779g0: Add INTC-EX pins, groups, and function
  pinctrl: renesas: r8a779g0: Remove unneeded separators
  pinctrl: renesas: r8a779h0: Add AVB MII pins and groups
  pinctrl: renesas: r8a779g0: Fix TPU suffixes
  pinctrl: renesas: r8a779g0: Fix TCLK suffixes
  pinctrl: renesas: r8a779g0: FIX PWM suffixes
  pinctrl: renesas: r8a779g0: Fix IRQ suffixes
  ...