linux.git/Documentation/devicetree/bindings/pinctrl, branch v4.20 Linux kernel source tree dt-bindings: pinctrl: bcm4708-pinmux: improve example binding 2018-10-16T07:43:34+00:00 Rafał Miłecki rafal@milecki.pl 2018-10-15T09:30:13+00:00 93d39737b29eaf1974bf850ccdc903b2418c800b Broadcom SoC pins are controlled using CRU ("Clock and Reset Unit" or "Central Resource Unit") registers. There are more CRU registers and functions so CRU should be represented as a separated block in DT. Moreover CRU is a sub-block of DMU ("Device Management Unit") so that one should also get its own node. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Broadcom SoC pins are controlled using CRU ("Clock and Reset Unit" or
"Central Resource Unit") registers. There are more CRU registers and
functions so CRU should be represented as a separated block in DT.

Moreover CRU is a sub-block of DMU ("Device Management Unit") so that
one should also get its own node.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Merge tag 'sh-pfc-for-v4.20-tag3' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 2018-10-10T09:15:33+00:00 Linus Walleij linus.walleij@linaro.org 2018-10-10T09:15:33+00:00 b0b378acde3da08663c580897ea91845489ecfc4 pinctrl: sh-pfc: Updates for v4.20 (take three) - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033) SoCs, - Add INTC-EX pin groups on R-Car E3. 
pinctrl: sh-pfc: Updates for v4.20 (take three)

  - Add support for the new RZ/N1D (R9A06G032) and RZ/N1S (R9A06G033)
    SoCs,
  - Add INTC-EX pin groups on R-Car E3.
dt-bindings: pinctrl: document Broadcom Northstar pin mux controller 2018-10-10T07:16:00+00:00 Rafał Miłecki rafal@milecki.pl 2018-09-26T19:31:02+00:00 3f9f82b3ffb8bfe01988c890e3a24328e9e1c1df Northstar has mux controller just like Northstar Plus and Northstar2. It's a bit different though (different registers & pins) so it requires its own binding. It's needed to allow other block bindings specify required mux setup. Signed-off-by: Rafał Miłecki <rafal@milecki.pl> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Northstar has mux controller just like Northstar Plus and Northstar2.
It's a bit different though (different registers & pins) so it requires
its own binding.

It's needed to allow other block bindings specify required mux setup.

Signed-off-by: Rafał Miłecki <rafal@milecki.pl>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: qcom: Add SDM660 pinctrl binding 2018-10-03T06:58:07+00:00 Craig Tatlor ctatlor97@gmail.com 2018-09-26T16:26:43+00:00 73ae1462b758f07d1209c913f4b1fbe47e0827b9 Add the binding for the TLMM pinctrl block found in the SDM660 platform. Signed-off-by: Craig Tatlor <ctatlor97@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add the binding for the TLMM pinctrl block found in the SDM660 platform.

Signed-off-by: Craig Tatlor <ctatlor97@gmail.com>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: renesas,rzn1-pinctrl: documentation 2018-10-02T10:16:39+00:00 Phil Edworthy phil.edworthy@renesas.com 2018-09-26T09:10:51+00:00 d6381fbbf2bcfd85206501072511e43a80cfc65f The Renesas RZ/N1 device family PINCTRL node description. Based on a patch originally written by Michel Pollet at Renesas. Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com> Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 
The Renesas RZ/N1 device family PINCTRL node description.

Based on a patch originally written by Michel Pollet at Renesas.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Merge tag 'sh-pfc-for-v4.20-tag2' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel 2018-10-01T11:21:58+00:00 Linus Walleij linus.walleij@linaro.org 2018-10-01T11:21:58+00:00 18887f31df122951b73be098e416fc871f426b0b pinctrl: sh-pfc: Updates for v4.20 (take two) - Add MSIOF pin groups on R-Car E3 and D3, - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs, - Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C, - Convert to SPDX license identifiers, - Small cleanups. 
pinctrl: sh-pfc: Updates for v4.20 (take two)

  - Add MSIOF pin groups on R-Car E3 and D3,
  - Add support for the new RZ/G1N (R8A7744) and RZ/G2E (R8A774C0) SoCs,
  - Add I2C4, DU0, QSPI0, SDHI2, and USB pin groups on RZ/G1C,
  - Convert to SPDX license identifiers,
  - Small cleanups.
dt-bindings: pinctrl: qcom: Add QCS404 pinctrl binding 2018-09-26T07:43:01+00:00 Bjorn Andersson bjorn.andersson@linaro.org 2018-09-24T22:17:47+00:00 9d8ea6beac3df23f505efaeb178768d50bc593af Add the binding for the TLMM pinctrl block found in the QCS404 platform. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add the binding for the TLMM pinctrl block found in the QCS404 platform.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support 2018-09-26T07:29:03+00:00 Vinod Koul vkoul@kernel.org 2018-09-25T00:06:56+00:00 ed80f6eb799a4b837de1095cca45de2286fb4837 Add support for the PMS405 GPIO support to the Qualcomm PMIC GPIO binding. Signed-off-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org> 
Add support for the PMS405 GPIO support to the Qualcomm PMIC GPIO
binding.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
dt-bindings: pinctrl: sh-pfc: Document r8a774c0 PFC support 2018-09-19T15:27:53+00:00 Fabrizio Castro fabrizio.castro@bp.renesas.com 2018-09-12T13:31:01+00:00 c382e8ba7c33b6dd64850a7d0f3ae19038f2fb1a Document PFC support for the R8A774C0 SoC. Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Biju Das <biju.das@bp.renesas.com> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 
Document PFC support for the R8A774C0 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Biju Das <biju.das@bp.renesas.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
dt-bindings: pinctrl: sh-pfc: Document r8a7744 PFC support 2018-09-19T15:26:18+00:00 Biju Das biju.das@bp.renesas.com 2018-09-11T10:30:04+00:00 a6a7d2c2dc668fb19bc16b4cda397cb1831df54d Document PFC support for the RZ/G1N (R8A7744) SoC. Signed-off-by: Biju Das <biju.das@bp.renesas.com> Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> 
Document PFC support for the RZ/G1N (R8A7744) SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Reviewed-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>