linux.git/Documentation/devicetree/bindings/phy, branch v6.16 Linux kernel source tree dt-bindings: phy: rockchip,inno-usb2phy: add rk3562 2025-05-14T11:20:39+00:00 Kever Yang kever.yang@rock-chips.com 2025-04-15T05:00:04+00:00 abf55cdf9c5e58bac1feaff2e21bec43b898746c Add compatible for the USB2 phy in the Rockchip RK3562 SoC. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add compatible for the USB2 phy in the Rockchip RK3562 SoC.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250415050005.52773-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible 2025-05-14T11:19:29+00:00 Heiko Stuebner heiko@sntech.de 2025-05-03T20:15:10+00:00 d78b565371314e48242cb9383d0f9d331119ab2e Add compatible for the USB2 phy in the Rockchip RK3036 SoC. Apart from some bits that got swapped around in the phy registers, the block is nearly the same as the one on the rk3128. Signed-off-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add compatible for the USB2 phy in the Rockchip RK3036 SoC.

Apart from some bits that got swapped around in the phy registers, the
block is nearly the same as the one on the rk3128.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250503201512.991277-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC 2025-05-14T11:14:59+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-04-14T14:57:27+00:00 9c4fbefc962dd13694b4a5051f432ed435c92220 Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC. RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it needs additional configuration to be done as compared RZ/G2L USB2.0 phy. To handle this difference a SoC specific compat string is added for RZ/V2H(P) SoC. Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets` property and has two clocks. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document USB2.0 phy bindings for RZ/V2H(P) ("R9A09gG57") SoC.

RZ/V2H(P) USB2.0 phy is similar to one found on the RZ/G2L SoC, but it
needs additional configuration to be done as compared RZ/G2L USB2.0 phy.
To handle this difference a SoC specific compat string is added for
RZ/V2H(P) SoC.

Like the RZ/G2L SoC, the RZ/V2H(P) USB2.0 PHY requires the `resets`
property and has two clocks.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family 2025-05-14T11:14:58+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-04-14T14:57:26+00:00 31eebeef8cdd4c9bddc9d34053cab6553616d0b7 The RZ/G2L family requires two clocks for USB2 PHY, which are already defined in the DTSI files. Add a constraint in the DT binding document to ensure validation with `dtbs_check`. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The RZ/G2L family requires two clocks for USB2 PHY, which are already
defined in the DTSI files. Add a constraint in the DT binding document
to ensure validation with `dtbs_check`.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250414145729.343133-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: samsung,usb3-drd-phy: add exynos2200 support 2025-05-14T10:43:37+00:00 Ivaylo Ivanov ivo.ivanov.ivanov1@gmail.com 2025-05-04T14:45:19+00:00 e4c9a7b475e5d0d9b2440ee48f91d1364eabd6cb Document support for Exynos2200. As the USBDRD 3.2 4nm controller consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will be handled by external drivers, define only the bus clocked used by the link controller. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document support for Exynos2200. As the USBDRD 3.2 4nm controller
consists of Synopsys eUSB2.0 phy and USBDP/SS combophy, which will
be handled by external drivers, define only the bus clocked used
by the link controller.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-3-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: add exynos2200 eusb2 phy support 2025-05-14T10:43:37+00:00 Ivaylo Ivanov ivo.ivanov.ivanov1@gmail.com 2025-05-04T14:45:18+00:00 59cf7546079e3d08d105369c48f8834970290082 Document the exynos2200 eUSB2 compatible. Unlike the currently documented Qualcomm SoCs, the driver doesn't make use of reset lines for reset control and uses more clocks. Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the exynos2200 eUSB2 compatible. Unlike the currently documented
Qualcomm SoCs, the driver doesn't make use of reset lines for reset
control and uses more clocks.

Signed-off-by: Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250504144527.1723980-2-ivo.ivanov.ivanov1@gmail.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: rockchip: Convert RK3399 PCIe PHY to schema 2025-05-14T10:16:28+00:00 Rob Herring (Arm) robh@kernel.org 2025-04-15T01:18:23+00:00 1d6fc048b86b76db73073ded8e84b0fd8757c908 Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the example to the GRF binding as that has the complete block. Signed-off-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Convert the Rockchip RK3399 PCIe PHY to DT schema format. Move the
example to the GRF binding as that has the complete block.

Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/20250415011824.2320039-1-robh@kernel.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: imx8mq-usb: add imx95 tuning support 2025-05-14T10:16:04+00:00 Xu Yang xu.yang_2@nxp.com 2025-04-30T09:45:00+00:00 7325e0995f414af1cfa38be965dc47248cb4ec45 The parameter value of below 3 properties are USB PHY specific. i.MX8MP and i.MX95 USB PHY has different meanings. This will enlarge parameters value and add constraints for them. - fsl,phy-tx-vref-tune-percent - fsl,phy-tx-rise-tune-percent - fsl,phy-comp-dis-tune-percent Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The parameter value of below 3 properties are USB PHY specific. i.MX8MP
and i.MX95 USB PHY has different meanings. This will enlarge parameters
value and add constraints for them.

 - fsl,phy-tx-vref-tune-percent
 - fsl,phy-tx-rise-tune-percent
 - fsl,phy-comp-dis-tune-percent

Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-2-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: imx8mq-usb: fix fsl,phy-tx-vboost-level-microvolt property 2025-05-14T10:16:04+00:00 Xu Yang xu.yang_2@nxp.com 2025-04-30T09:44:59+00:00 5b3a91b207c00a8d27f75ce8aaa9860844da72c8 The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in register PHY_CTRL3 bit[31:29]. 011: Corresponds to a launch amplitude of 1.12 V. 010: Corresponds to a launch amplitude of 1.04 V. 000: Corresponds to a launch amplitude of 0.88 V. After updated: 011: Corresponds to a launch amplitude of 0.844 V. 100: Corresponds to a launch amplitude of 1.008 V. 101: Corresponds to a launch amplitude of 1.156 V. This will correct it accordingly. Fixes: b2e75563dc39 ("dt-bindings: phy: imx8mq-usb: add phy tuning properties") Cc: stable@vger.kernel.org Reviewed-by: Jun Li <jun.li@nxp.com> Signed-off-by: Xu Yang <xu.yang_2@nxp.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The ticket TKT0676370 shows the description of TX_VBOOST_LVL is wrong in
register PHY_CTRL3 bit[31:29].

  011: Corresponds to a launch amplitude of 1.12 V.
  010: Corresponds to a launch amplitude of 1.04 V.
  000: Corresponds to a launch amplitude of 0.88 V.

After updated:

  011: Corresponds to a launch amplitude of 0.844 V.
  100: Corresponds to a launch amplitude of 1.008 V.
  101: Corresponds to a launch amplitude of 1.156 V.

This will correct it accordingly.

Fixes: b2e75563dc39 ("dt-bindings: phy: imx8mq-usb: add phy tuning properties")
Cc: stable@vger.kernel.org
Reviewed-by: Jun Li <jun.li@nxp.com>
Signed-off-by: Xu Yang <xu.yang_2@nxp.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250430094502.2723983-1-xu.yang_2@nxp.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: mediatek,tphy: Add support for MT6893 2025-05-14T08:44:35+00:00 AngeloGioacchino Del Regno angelogioacchino.delregno@collabora.com 2025-04-16T12:02:20+00:00 1b1e949924fb59e98d9401681b139e92e75686ac Add a compatible string for the MediaTek Dimensity 1200 (MT6893) SoC: this chip integrates a MediaTek generic T-PHY version 2. Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add a compatible string for the MediaTek Dimensity 1200 (MT6893)
SoC: this chip integrates a MediaTek generic T-PHY version 2.

Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250416120220.147798-2-angelogioacchino.delregno@collabora.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>