linux.git/Documentation/devicetree/bindings/phy, branch v6.15 Linux kernel source tree dt-bindings: phy: rockchip: Add rk3562 naneng-combophy compatible 2025-03-16T17:02:23+00:00 Kever Yang kever.yang@rock-chips.com 2025-02-27T11:08:35+00:00 86ae168934098be744cd5a8470544165f0054d0b rk3562 use the same Naneng Combo Phy driver as rk3568. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250227110836.2343158-1-kever.yang@rock-chips.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
rk3562 use the same Naneng Combo Phy driver as rk3568.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20250227110836.2343158-1-kever.yang@rock-chips.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: Add Rockchip MIPI C-/D-PHY schema 2025-03-16T16:40:46+00:00 Heiko Stuebner heiko.stuebner@cherry.de 2025-03-13T13:40:31+00:00 301587cf4e771aca8c5ee05a6ba8d7d8f548e478 Add dt-binding schema for the MIPI C-/D-PHY found on Rockchip RK3588 SoCs. Tested-by: Daniel Semkowicz <dse@thaumatec.com> Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com> Tested-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de> Link: https://lore.kernel.org/r/20250313134035.278133-2-heiko@sntech.de Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add dt-binding schema for the MIPI C-/D-PHY found on
Rockchip RK3588 SoCs.

Tested-by: Daniel Semkowicz <dse@thaumatec.com>
Tested-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Tested-by: Quentin Schulz <quentin.schulz@cherry.de>
Reviewed-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Heiko Stuebner <heiko.stuebner@cherry.de>
Link: https://lore.kernel.org/r/20250313134035.278133-2-heiko@sntech.de
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: Document the QCS8300 QMP PCIe PHY Gen4 x2 2025-03-11T11:25:52+00:00 Ziyue Zhang quic_ziyuzhan@quicinc.com 2025-03-10T06:30:56+00:00 e46e59b77a9e6f322ef1ad08a8874211f389cf47 Document the QMP PCIe PHY on the QCS8300 platform. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com> Link: https://lore.kernel.org/r/20250310063103.3924525-2-quic_ziyuzhan@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the QMP PCIe PHY on the QCS8300 platform.

Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Ziyue Zhang <quic_ziyuzhan@quicinc.com>
Link: https://lore.kernel.org/r/20250310063103.3924525-2-quic_ziyuzhan@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,sc8280xp-qmp-ufs-phy: document the SM8750 QMP UFS PHY 2025-03-11T11:24:46+00:00 Nitin Rawat quic_nitirawa@quicinc.com 2025-03-10T21:12:29+00:00 12185bc38f7667b1d895b2165a8a47335a4cf31b Document the QMP UFS PHY on the SM8750 Platform. Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com> Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-1-0dfdd6823161@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the QMP UFS PHY on the SM8750 Platform.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitin Rawat <quic_nitirawa@quicinc.com>
Link: https://lore.kernel.org/r/20250310-sm8750_ufs_master-v2-1-0dfdd6823161@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,uniphy-pcie: Document PCIe uniphy 2025-03-11T11:21:01+00:00 Nitheesh Sekar quic_nsekar@quicinc.com 2025-02-20T09:42:45+00:00 a2e934885c82912caf3f72b9511ef626f3619e3d Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com> Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com> Link: https://lore.kernel.org/r/20250220094251.230936-2-quic_varada@quicinc.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Document the Qualcomm UNIPHY PCIe 28LP present in IPQ5332.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Nitheesh Sekar <quic_nsekar@quicinc.com>
Signed-off-by: Varadarajan Narayanan <quic_varada@quicinc.com>
Link: https://lore.kernel.org/r/20250220094251.230936-2-quic_varada@quicinc.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: document Allwinner A523 USB-2.0 PHY 2025-03-10T07:14:27+00:00 Andre Przywara andre.przywara@arm.com 2025-03-07T00:57:04+00:00 1f7af7f3c353ae3b384a66a82c5074ac28901160 The Allwinner A523 SoC contains a USB-2.0 PHY fully compatible to the one used in the D1/T113s SoCs. This PHY controls the two USB-2.0 ports, there is a separate and quite different PHY for the USB-3.0 port. Add the new compatible string, with a fallback to the D1 version. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20250307005712.16828-8-andre.przywara@arm.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
The Allwinner A523 SoC contains a USB-2.0 PHY fully compatible to the
one used in the D1/T113s SoCs. This PHY controls the two USB-2.0 ports,
there is a separate and quite different PHY for the USB-3.0 port.

Add the new compatible string, with a fallback to the D1 version.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20250307005712.16828-8-andre.przywara@arm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: Add ExynosAutov920 UFS PHY bindings 2025-02-13T18:03:40+00:00 Sowon Na sowon.na@samsung.com 2024-12-26T03:11:36+00:00 0ee54dcfe76760a65d86437f66df7f93b8b81903 Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC. Signed-off-by: Sowon Na <sowon.na@samsung.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com> Link: https://lore.kernel.org/r/20241226031142.1764652-2-sowon.na@samsung.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
Add samsung,exynosautov920-ufs-phy compatible for ExynosAuto v920 SoC.

Signed-off-by: Sowon Na <sowon.na@samsung.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Link: https://lore.kernel.org/r/20241226031142.1764652-2-sowon.na@samsung.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: samsung,usb3-drd-phy: gs101: require Type-C properties 2025-02-13T17:12:52+00:00 André Draszik andre.draszik@linaro.org 2024-12-06T16:31:02+00:00 c38528812c2e9b05fe8b5fd1f66cf4c75835a38e orientation-switch is the standard declaration to inform the Type-C mux layer that a remote-endpoint is capable of processing orientation change messages. The USB PHY on gs101 needs to be configured based on the orientation of the connector. For that the DTS needs a link between the phy's port and a TCPCi, and we'll need to inform the phy driver that it should handle the orientation (register a handler). Update the schema to enforce that by requiring the orientation-switch and port properties on gs101 (only). We disallow orientation-switch on all other supported platforms, since other versions of this phy (or its system integration) don't currently support or even need it. Even though this new required gs101 property is an ABI break, the intention for the driver is to behave as before if it's missing (meaning for gs101 it will work in SS mode in one orientation only). Other platforms are not affected. Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-2-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
orientation-switch is the standard declaration to inform the Type-C mux
layer that a remote-endpoint is capable of processing orientation
change messages.

The USB PHY on gs101 needs to be configured based on the orientation of
the connector. For that the DTS needs a link between the phy's port and
a TCPCi, and we'll need to inform the phy driver that it should handle
the orientation (register a handler).

Update the schema to enforce that by requiring the orientation-switch
and port properties on gs101 (only). We disallow orientation-switch on
all other supported platforms, since other versions of this phy (or its
system integration) don't currently support or even need it.

Even though this new required gs101 property is an ABI break, the
intention for the driver is to behave as before if it's missing
(meaning for gs101 it will work in SS mode in one orientation only).
Other platforms are not affected.

Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-2-f5961268b149@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: samsung,usb3-drd-phy: add blank lines between DT properties 2025-02-13T17:12:52+00:00 André Draszik andre.draszik@linaro.org 2024-12-06T16:31:01+00:00 642b1ed4cd184d5c2e5814c220bb93453492644d In [1], Rob pointed out that we should really be separating properties with blank lines in between, which is universal style. Only where properties are booleans, empty lines are not required. Do so. Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/ [1] Reviewed-by: Peter Griffin <peter.griffin@linaro.org> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: André Draszik <andre.draszik@linaro.org> Tested-by: Will McVicker <willmcvicker@google.com> Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-1-f5961268b149@linaro.org Signed-off-by: Vinod Koul <vkoul@kernel.org> 
In [1], Rob pointed out that we should really be separating properties
with blank lines in between, which is universal style. Only where
properties are booleans, empty lines are not required.

Do so.

Link: https://lore.kernel.org/all/20240711212359.GA3023490-robh@kernel.org/ [1]
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: André Draszik <andre.draszik@linaro.org>
Tested-by: Will McVicker <willmcvicker@google.com>
Link: https://lore.kernel.org/r/20241206-gs101-phy-lanes-orientation-phy-v4-1-f5961268b149@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>
dt-bindings: phy: qcom,qmp-pcie: Drop reset number constraints 2025-02-10T17:08:55+00:00 Konrad Dybcio konrad.dybcio@oss.qualcomm.com 2025-02-03T14:43:21+00:00 f67f8c61b7fd3f72cf716b3845211e69265d13bd (Almost?) all QMP PHYs come with both a "full reset" ("phy") and a "retain certain registers" one ("phy_nocsr"). Drop the maxItems=1 constraint for resets and reset_names as we go ahead and straighten out the DT usage. After that's done (which will involve modifying some clock drivers etc.), we may set *min*Items to 2, bar some possible exceptions. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-2-72cd4cdc767b@oss.qualcomm.com Signed-off-by: Vinod Koul <vkoul@kernel.org> 
(Almost?) all QMP PHYs come with both a "full reset" ("phy") and a
"retain certain registers" one ("phy_nocsr").

Drop the maxItems=1 constraint for resets and reset_names as we go
ahead and straighten out the DT usage. After that's done (which
will involve modifying some clock drivers etc.), we may set
*min*Items to 2, bar some possible exceptions.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250203-topic-x1p4_dts-v2-2-72cd4cdc767b@oss.qualcomm.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>