linux.git/Documentation/devicetree/bindings/phy, branch v6.11

dt-bindings: phy: airoha: Add dtime and Rx AEQ IO registers

2024-07-02T13:24:28+00:00

Introduce Tx-Rx detection time and Rx AEQ mappings in Airoha EN7581
PCIe-PHY binding. This change is not introducing any backward compatibility
issue since the EN7581 dts is not upstream yet.

Signed-off-by: Lorenzo Bianconi 
Acked-by: Conor Dooley 
Link: https://lore.kernel.org/r/a018329ff9678f3360bc6381294f95c62d34f3e3.1719682943.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul

dt-bindings: phy: rockchip-emmc-phy: Convert to dtschema

2024-07-02T13:24:01+00:00

Convert txt bindings of Rockchip EMMC PHY to dtschema to allow
for validation.

Signed-off-by: Shresth Prasad 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20240620212806.3011-2-shresthprasad7@gmail.com
Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,qmp-usb: fix spelling error

2024-07-02T13:23:04+00:00

Correct the spelling error, changing 'com' to 'qcom'.

Cc: stable@vger.kernel.org
Fixes: f75a4b3a6efc ("dt-bindings: phy: qcom,qmp-usb: Add QDU1000 USB3 PHY")
Signed-off-by: Yijie Yang 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20240624021916.2033062-1-quic_yijiyang@quicinc.com
Signed-off-by: Vinod Koul

dt-bindings: phy: samsung,usb3-drd-phy: add gs101 compatible

2024-07-02T13:22:04+00:00

Add a dedicated google,gs101-usb31drd-phy compatible for Google Tensor
gs101 SoC.

It needs additional clocks enabled for register access, and additional
memory regions (PCS & PMA) are required for successful configuration.

It also requires various power supplies (regulators) for the internal
circuitry to work. The required voltages are:
* pll-supply: 0.85V
* dvdd-usb20-supply: 0.85V (+10%, -7%)
* vddh-usb20-supply: 1.8V (+10%, -7%)
* vdd33-usb20-supply: 3.3V (+10%, -7%)
* vdda-usbdp-supply: 0.85V
* vddh-usbdp-supply: 1.8V

Signed-off-by: André Draszik 
Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: Peter Griffin 
Link: https://lore.kernel.org/r/20240617-usb-phy-gs101-v3-1-b66de9ae7424@linaro.org
Signed-off-by: Vinod Koul

dt-bindings: phy: airoha: Add PCIe PHY controller

2024-06-20T16:29:21+00:00

Introduce device-tree binding documentation for Airoha EN7581 PCIe PHY
controller.

Reviewed-by: Krzysztof Kozlowski 
Reviewed-by: AngeloGioacchino Del Regno 
Signed-off-by: Lorenzo Bianconi 
Link: https://lore.kernel.org/r/656133f865433c1d02f00a3abbb1aa9312d2a24e.1718485860.git.lorenzo@kernel.org
Signed-off-by: Vinod Koul

dt-bindings: phy: Add i.MX8Q HSIO SerDes PHY binding

2024-06-15T12:22:01+00:00

Add i.MX8QM and i.MX8QXP HSIO SerDes PHY binding.
Introduce one HSIO configuration 'fsl,hsio-cfg', which need be set at
initialization according to board design.

Signed-off-by: Richard Zhu 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/1716962565-2084-2-git-send-email-hongxing.zhu@nxp.com
Signed-off-by: Vinod Koul

dt-bindings: phy: Add starfive,jh7110-dphy-tx

2024-06-15T12:08:30+00:00

StarFive SoCs like the jh7110 use a MIPI D-PHY TX
controller based on a M31 IP. Add a binding for it.

Signed-off-by: Shengyang Chen 
Reviewed-by: Krzysztof Kozlowski 
Link: https://lore.kernel.org/r/20240418035020.47876-2-shengyang.chen@starfivetech.com
Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,usb-hs-phy: Add compatible

2024-06-15T11:49:49+00:00

Adds qcom,usb-hs-phy-msm8660 compatible

Used by HP Touchpad (tenderloin) for example.

Signed-off-by: Herman van Hazendonk 
Reviewed-by: Rob Herring (Arm) 
Link: https://lore.kernel.org/r/20240417065454.3599824-1-github.com@herrie.org
Signed-off-by: Vinod Koul

dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: drop second output clock name

2024-06-15T11:31:17+00:00

There is no need to specify exact name for the second (AUX) output
clock. It has never been used for the lookups based on the system clock
name. Partially revert commit 72bea132f368 ("dt-bindings: phy:
qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs"),
returning compatibility with the existing device tree: reduce
clock-output-names to always contain a single entry.

Fixes: 72bea132f368 ("dt-bindings: phy: qcom,sc8280xp-qmp-pcie-phy: document PHY AUX clock on SM8[456]50 SoCs")
Acked-by: Krzysztof Kozlowski 
Signed-off-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20240614-fix-pcie-phy-compat-v3-2-730d1811acf4@linaro.org
Signed-off-by: Vinod Koul

dt-bindings: phy: g12a-usb2-phy: add optional power-domains

2024-06-12T17:46:15+00:00

On newer SoCs, the USB2 PHY can require a power-domain to operate,
add it as optional.

Signed-off-by: Neil Armstrong 
Acked-by: Rob Herring (Arm) 
Link: https://lore.kernel.org/r/20240605-topic-amlogic-upstream-bindings-fixes-power-domains-phy-v1-1-c819b0ecd8c8@linaro.org
Signed-off-by: Vinod Koul