linux.git/Documentation/devicetree/bindings/phy, branch v4.12

phy: rockchip-usb: Add vbus regulator support.

2017-04-10T11:13:41+00:00

On rockchip devices vbus is supplied by a separate power supply, often
through a regulator. Add support for describing the the regulator in
device-tree following the same convention as several other usb phy's.

Signed-off-by: Sjoerd Simons 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add support for QMP phy

2017-04-10T11:13:41+00:00

Qualcomm chipsets have QMP phy controller that provides
support to a number of controller, viz. PCIe, UFS, and USB.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam 
Reviewed-by: Stephen Boyd 
Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy: Add support for QUSB2 phy

2017-04-10T11:13:41+00:00

Qualcomm chipsets have QUSB2 phy controller that provides
HighSpeed functionality for DWC3 controller.
Adding dt binding information for the same.

Signed-off-by: Vivek Gautam 
Reviewed-by: Stephen Boyd 
Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy-rockchip-inno-usb2: add assign clock property in usb2-phy node

2017-04-10T11:13:41+00:00

On some platform such as RK3328, the 480m clock may need to assign
clock parent in dts in stead of clock driver. So this patch add
property of assigned-clocks and assigned-clock-parents to assign
parent for 480m clock.

Signed-off-by: Meng Dongyang 
Acked-by: Rob Herring 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Kishon Vijay Abraham I

dt-bindings: phy-mt65xx-usb: add support for new version phy

2017-04-10T11:13:40+00:00

add a new compatible string for "mt2712", and move reference clock
into each port node;

Signed-off-by: Chunfeng Yun 
Acked-by: Rob Herring 
Signed-off-by: Kishon Vijay Abraham I

dt: bindings: add pmu0 regs for USB PHYs on Allwinner H3/V3s/A64

2017-04-10T11:12:57+00:00

Allwinner H3/V3s/A64 SoCs have a special USB PHY0 that can route to two
controllers: one is MUSB and the other is a EHCI/OHCI pair.

When it's routed to EHCI/OHCI pair, it will needs a "pmu0" regs to
tweak, like other EHCI/OHCI pairs in Allwinner SoCs.

Add this to the binding of USB PHYs on Allwinner H3/V3s/A64.

Signed-off-by: Icenowy Zheng 
Acked-by: Chen-Yu Tsai 
Signed-off-by: Kishon Vijay Abraham I

Revert "dt-bindings: phy: Add documentation for NSP USB3 PHY"

2017-03-09T09:59:44+00:00

This reverts commit c8ca631f9480 ("dt-bindings: phy: Add documentation
for NSP USB3 PHY") to match reverting commit adding the new PHY driver.
Please note we revert this commit before it reached stable release.

If new compatible string is needed it should be added to the existing
bcm-ns-usb3-phy.txt which already describes this PHY.

Acked-by: Jon Mason 
Acked-by: Rob Herring 
Signed-off-by: Rafał Miłecki

Merge tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

2017-02-23T19:53:22+00:00

Pull PCI updates from Bjorn Helgaas:

 - add ASPM L1 substate support

 - enable PCIe Extended Tags when supported

 - configure PCIe MPS settings on iProc, Versatile, X-Gene, and Xilinx

 - increase VPD access timeout

 - add ACS quirks for Intel Union Point, Qualcomm QDF2400 and QDF2432

 - use new pci_irq_alloc_vectors() in more drivers

 - fix MSI affinity memory leak

 - remove unused MSI interfaces and update documentation

 - remove unused AER .link_reset() callback

 - avoid pci_lock / p->pi_lock deadlock seen with perf

 - serialize sysfs enable/disable num_vfs operations

 - move DesignWare IP from drivers/pci/host/ to drivers/pci/dwc/ and
   refactor so we can support both hosts and endpoints

 - add DT ECAM-like support for HiSilicon Hip06/Hip07 controllers

 - add Rockchip system power management support

 - add Thunder-X cn81xx and cn83xx support

 - add Exynos 5440 PCIe PHY support

* tag 'pci-v4.11-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (93 commits)
  PCI: dwc: Remove dependency of designware on CONFIG_PCI
  PCI: dwc: Add CONFIG_PCIE_DW_HOST to enable PCI dwc host
  PCI: dwc: Split pcie-designware.c into host and core files
  PCI: dwc: designware: Fix style errors in pcie-designware.c
  PCI: dwc: designware: Parse "num-lanes" property in dw_pcie_setup_rc()
  PCI: dwc: all: Split struct pcie_port into host-only and core structures
  PCI: dwc: designware: Get device pointer at the start of dw_pcie_host_init()
  PCI: dwc: all: Rename cfg_read/cfg_write to read/write
  PCI: dwc: all: Use platform_set_drvdata() to save private data
  PCI: dwc: designware: Move register defines to designware header file
  PCI: dwc: Use PTR_ERR_OR_ZERO to simplify code
  PCI: dra7xx: Group PHY API invocations
  PCI: dra7xx: Enable MSI and legacy interrupts simultaneously
  PCI: dra7xx: Add support to force RC to work in GEN1 mode
  PCI: dra7xx: Simplify probe code with devm_gpiod_get_optional()
  PCI: Move DesignWare IP support to new drivers/pci/dwc/ directory
  PCI: exynos: Support the PHY generic framework
  Documentation: binding: Modify the exynos5440 PCIe binding
  phy: phy-exynos-pcie: Add support for Exynos PCIe PHY
  Documentation: samsung-phy: Add exynos-pcie-phy binding
  ...

Documentation: samsung-phy: Add exynos-pcie-phy binding

2017-02-21T13:48:40+00:00

Add the exynos-pcie-phy binding for Exynos PCIe PHY.  This is for using
generic PHY framework.

Signed-off-by: Jaehoon Chung 
Signed-off-by: Bjorn Helgaas 
Acked-by: Rob Herring

dt-bindings: phy: Add documentation for NSP USB3 PHY

2017-01-27T07:36:53+00:00

Add documentation for USB3 PHY available in Northstar plus SoC

Signed-off-by: Yendapally Reddy Dhananjaya Reddy 
Signed-off-by: Kishon Vijay Abraham I