- Distinguish Tegra264 C0 PCIe controller for internal GPU from C1-C5 controllers so the unit address matches the first 'reg' entry (Thierry Reding) - Add Tegra264 Root Port stanzas to prepare for generic WAKE# handling (Thierry Reding) - Add NVIDIA Tegra264 driver (Thierry Reding) * pci/controller/tegra264: PCI: tegra264: Add Tegra264 support dt-bindings: PCI: tegra264: Switch to PCIe Root Port bindings dt-bindings: PCI: tegra264: Strictly distinguish C0 from C1-C5
- Add DT binding and driver support for RZ/V2H(P) SoC, which contains two PCIe controllers, configured either as a single x4 link or two independent x2 link controllers (Lad Prabhakar) * pci/controller/rzg3s-host: PCI: rzg3s-host: Add support for RZ/V2H(P) SoC PCI: rzg3s-host: Prepare System Controller handling for multiple controllers PCI: rzg3s-host: Use shared reset controls for power domain resets dt-bindings: PCI: renesas,r9a08g045-pcie: Add RZ/V2H(P) support
- Add 'core', 'dbi', and 'aux' clocks to DT binding and manage them in the driver (Jia Wang) - Use module_platform_driver() since this may be built as a module, though not removable because IRQs can't be safely disposed (Jia Wang) * pci/controller/dwc-ultrarisc: PCI: ultrarisc: Use module_platform_driver() PCI: ultrarisc: Get and enable DP1000 PCIe controller clocks dt-bindings: PCI: ultrarisc: Add required DP1000 PCIe clocks
- Add DT binding and driver support for Hawi SoC (Matthew Leung) - Skip PERST# GPIOs provided by downstream PCIe devices, which should be handled by drivers of those devices (Manivannan Sadhasivam) - Stop advertising Attention Button Present (no Qcom SoCs support Attention Buttons) so pciehp can use Presence Detect Changed events (Qiang Yu) * pci/controller/dwc-qcom: PCI: qcom: Clear Attention Button Present in Slot Capabilities PCI: qcom: Rename qcom_pcie_set_slot_nccs() to qcom_pcie_set_slot_cap() PCI: qcom: Skip PERST# GPIOs provided by downstream PCIe devices PCI: qcom: Add support for Hawi dt-bindings: PCI: qcom: Document Hawi and Maili PCIe Controllers
- Add qcom IPQ9650 compatible with global interrupt (Kathiravan Thirumoorthy) - Add qcom IPQ5210 compatible with IPQ9574 fallback (Varadarajan Narayanan) - Add imx6 intr/aer/pme interrupt lines for i.MX95 (Richard Zhu) - Add mediatek-gen3 'memory-region' for restricted DMA buffer (Chen-Yu Tsai) - Add rcar-gen4-pci-host optional 'msi-parent' for GIT ITS (Marek Vasut) - Correct some white-space issues (Krzysztof Kozlowski) * pci/dt-binding: dt-bindings: PCI: Correct white-space style dt-bindings: PCI: rcar-gen4-pci-host: Document optional msi-parent dt-bindings: PCI: mediatek-gen3: Allow memory-region for restricted DMA buffer dt-bindings: PCI: mediatek-gen3: Add support for MT8189 SoC dt-bindings: PCI: imx6q-pcie: Add i.MX95 optional intr/aer/pme interrupts dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ5210 compatible dt-bindings: PCI: qcom,pcie-ipq9574: Add IPQ9650 compatible
Switch to using the PCIe Root Port bindings in preparation for using the standard WAKE# handling. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260814-tegra264-pcie-v10-2-05d08c592b05@nvidia.com
Instead of using the ECAM registers as the first entry, strictly make a distinction between C0 and C1-C5. This is needed because otherwise the unit address doesn't match the first "reg" entry. The ordering of these nodes cannot be changed to follow the ECAM addresses because that would put them outside of their "control bus" hierarchy since the ECAM address space is a global one outside of any of the control busses. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260814-tegra264-pcie-v10-1-05d08c592b05@nvidia.com
Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style. No
functional changes.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260801195517.235161-2-krzysztof.kozlowski@oss.qualcomm.com
Require DP1000 PCIe controller nodes to provide clocks and clock-names,
using the standard DesignWare clock names "core", "dbi", and "aux".
Fixes: d9ff07f45955 ("dt-bindings: PCI: Add UltraRISC DP1000 PCIe controller")
Signed-off-by: Jia Wang <wangjia@ultrarisc.com>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://patch.msgid.link/20260731-ultrarisc-pci-clk-v4-1-d738b491e49a@ultrarisc.com
The R-Car Gen4 PCIe controller can optionally use GIC ITS as an MSI controller. This configuration is described in DT by setting msi-parent DT property in the PCIe controller node. Document this configuration. Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20260720015505.314957-1-marek.vasut+renesas@mailbox.org