Pull SoC devicetree updates from Arnd Bergmann:
 "A number of SoC platforms are adding modernized variants of their
  already supported chips time, with a total of 12 new SoCs, and two
  older SoC getting removed:

   - Qualcomm Glymur is a compute SoC using 18 Oryon-2 CPU cores
   - Qualcomm Mahua is a variant of Glymur with only 12 CPU cores, but
     largely identical.
   - Qualcomm Eliza is an embeded platform for mobile phone (SM7750) and
     IOT (QC7790S/M) workloads
   - Qualcomm IPQ5210 is a wireless networking SoC using Cortex-A53
     cores
   - Qualcomm apq8084 and ipq806x had only rudimentary support but no
     actual products using them, so they are now gone.
   - Axis ARTPEC-9 is a follow-up to the ARTPEC-8 embedded SoC, using
     the Samsung SoC platform but now with Cortex-A55 cores
   - ARM Zena is a virtual platform in FVP using Cortex-A720AE cores,
     with additional versions planned to be merged in the future.
   - ARM corstone-1000-a320 is a reference platform for IOT, using
     low-end Cortex-A320 cores
   - Microchip LAN9691 is an updated 64-bit variant of the arm32 lan966x
     series of networking SoCs
   - Microchip PIC64GX is an embedded RISC-V chip using SIFIVE U54 CPU
     cores
   - Rockchip RV1103B is the low-end 32-bit single-core vision processor
   - Renesas RZ/G3L (r9a08g046) is an industrial embedded chip using
     Cortex-A55 cores, similar to the G3E and G3S variants we already
     supported.
   - NXP S32N79 is an automotive SoC using Cortex-A78AE cores, a
     significant upgrade from the older S32V and S32G series

  These all come with at least one reference board or an initial product
  using these, in total there are 67 newly added boards. The ones for
  already supported SoCs are:

   - Two more Aspeed BMC based boards
   - Three older tablets based on 32-bit OMAP4 and Exynos5 SoCs
   - One Set-top-box based on Allwinner H6
   - 22 additional industrial/embedded boards using 64-bit NXP i.MX8M or
     i.MX9 SoCs
   - 20 Qualcomm SoC based machines across all possible markets:
     workstation, gaming, laptop, phone, networking, reference, ...
   - Three more Rockchips rk35xx based boards
   - Four variants of the Toradex Verdin using TI AM62

  Other notable bits are:

   - A cleanup for the 32-bit Tegra paz00 board moved the last board
     specific code on Tegra into equivalent dts syntax.
   - There continues to be a significant number of fixes for static
     checking of dtc syntax, but it feels like this is slowing down,
     hopefully getting into a state where most known issues are
     addressed
   - Additional hardware support for many existing boards across SoC
     families, notably Qualcomm, Broadcom, i.MX2, i.MX6, Rockchips,
     STM32, Mediatek, Tegra, TI and Microchip"

* tag 'soc-dt-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (841 commits)
  arm64: dts: ti: k3: Use memory-region-names for r5f
  ARM: dts: imx: Add DT overlays for DH i.MX6 DHCOM SoM and boards
  ARM: dts: imx6sx: remove fallback compatible string fsl,imx28-lcdif
  ARM: dts: imx25: rename node name tcq to touchscreen
  ARM: dts: imx: b850v3: Disable unused usdhc4
  ARM: dts: imx: b850v3: Define GPIO line names
  ARM: dts: imx: b850v3: Use alphabetical sorting
  ARM: dts: imx: bx50v3: Configure phy-mode to eliminate a warning
  ARM: dts: imx: bx50v3: Configure switch PHY max-speed to 100Mbps
  ARM: dts: imx7ulp: Add CPU clock and OPP table support
  ARM: dts: imx7-mba7: Deassert BOOT_EN after boot
  ARM: dts: tqma7: add boot phase properties
  ARM: dts: imx7s: add boot phase properties
  ARM: dts: tqma6ul[l]: correct spelling of TQ-Systems
  ARM: dts: mba6ulx: add boot phase properties
  ARM: dts: imx6ul[l]-tqma6ul[l]: add boot phase properties
  ARM: dts: imx6ul/imx6ull: add boot phase properties
  ARM: dts: imx6qdl-mba6: add boot phase properties
  ARM: dts: imx6qdl-tqma6: add boot phase properties
  ARM: dts: imx6qdl: add boot phase properties
  ...

- Assert (not deassert) resets in probe error path (John Madieu)

- Assert resets in suspend path in reverse order they were deasserted
  during probe (John Madieu)

- Rework inbound window algorithm to prevent mapping more than intended
  region and enforce alignment on size, to prepare for RZ/G3E support (John
  Madieu)

- Fix renesas,r9a08g045s33-pcie 'serr_cor' typo and convert properties from
  'description' to 'const' for better validation (John Madieu)

- Add RZ/G3E to DT binding and to driver (John Madieu)

* pci/controller/rzg3s-host:
  PCI: rzg3s-host: Add support for RZ/G3E PCIe controller
  PCI: rzg3s-host: Add PCIe Gen3 (8.0 GT/s) link speed support
  PCI: rzg3s-host: Explicitly set class code for RZ/G3E compatibility
  PCI: rzg3s-host: Add SoC-specific configuration and initialization callbacks
  PCI: rzg3s-host: Make configuration reset lines optional
  PCI: rzg3s-host: Make SYSC register offsets SoC-specific
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Document RZ/G3E SoC
  dt-bindings: PCI: renesas,r9a08g045s33-pcie: Fix naming properties
  PCI: rzg3s-host: Rework inbound window algorithm for supporting RZ/G3E SoC
  PCI: rzg3s-host: Reorder reset assertion during suspend
  PCI: rzg3s-host: Fix reset handling in probe error path

# Conflicts:
#	drivers/pci/controller/pcie-rzg3s-host.c

- Poll less aggressively and non-atomically for PME_TO_Ack during
  transition to L2 (Vidya Sagar)

- Increase LTSSM poll time on surprise link down (Manikanta Maddireddy)

- Disable LTSSM after transition to Detect on surprise link down to stop
  toggling between Polling and Detect (Manikanta Maddireddy)

- Don't force the device into the D0 state before L2 when suspending or
  shutting down the controller (Vidya Sagar)

- Disable PERST# IRQ only in Endpoint mode because it's not registered in
  Root Port mode (Manikanta Maddireddy)

- Handle 'nvidia,refclk-select' as optional (Vidya Sagar)

- Disable direct speed change in Endpoint mode so link speed change is
  controlled by the host (Vidya Sagar)

- Set LTR values before link up to avoid bogus LTR messages with 0 latency
  (Vidya Sagar)

- Allow system suspend when the Endpoint link is down (Vidya Sagar)

- During remove, free resources allocated during Endpoint .probe() (Vidya
  Sagar)

- Use DWC IP core version, not Tegra custom values, to avoid DWC core
  version check warnings (Manikanta Maddireddy)

- Apply ECRC workaround to devices based on DesignWare 5.00a as well
  as 4.90a (Manikanta Maddireddy)

- Disable PM Substate L1.2 in Endpoint mode to work around Tegra234 erratum
  (Vidya Sagar)

- Delay post-PERST# cleanup until core is powered on to avoid CBB timeout
  (Manikanta Maddireddy)

- Assert CLKREQ# so switches that forward it to their downstream side can
  bring up those links successfully (Vidya Sagar)

- Calibrate pipe to UPHY for Endpoint mode to reset stale PLL state from
  any previous bad link state (Vidya Sagar)

- Remove IRQF_ONESHOT flag from Endpoint interrupt registration so DMA
  driver and Endpoint controller driver can share the interrupt line (Vidya
  Sagar)

- Enable DMA interrupt to support DMA in both Root Port and Endpoint modes
  (Vidya Sagar)

- Enable hardware link retraining after link goes down in Endpoint mode
  (Vidya Sagar)

- Add DT binding and driver support for core clock monitoring (Vidya Sagar)

* pci/controller/dwc-tegra194:
  PCI: tegra194: Add core monitor clock support
  dt-bindings: PCI: tegra194: Add monitor clock support
  PCI: tegra194: Enable hardware hot reset mode in Endpoint mode
  PCI: tegra194: Enable DMA interrupt
  PCI: tegra194: Remove IRQF_ONESHOT flag during Endpoint interrupt registration
  PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode
  PCI: tegra194: Assert CLKREQ# explicitly by default
  PCI: tegra194: Fix CBB timeout caused by DBI access before core power-on
  PCI: tegra194: Disable L1.2 capability of Tegra234 EP
  PCI: dwc: Apply ECRC workaround to DesignWare 5.00a as well
  PCI: tegra194: Use DWC IP core version
  PCI: tegra194: Free up Endpoint resources during remove()
  PCI: tegra194: Allow system suspend when the Endpoint link is not up
  PCI: tegra194: Set LTR message request before PCIe link up in Endpoint mode
  PCI: tegra194: Disable direct speed change for Endpoint mode
  PCI: tegra194: Use devm_gpiod_get_optional() to parse "nvidia,refclk-select"
  PCI: tegra194: Disable PERST# IRQ only in Endpoint mode
  PCI: tegra194: Don't force the device into the D0 state before L2
  PCI: tegra194: Disable LTSSM after transition to Detect on surprise link down
  PCI: tegra194: Increase LTSSM poll time on surprise link down
  PCI: tegra194: Fix polling delay for L2 state

- Add DT binding and driver for ESWIN PCIe Root Complex (Senchuan Zhang)

* pci/controller/dwc-eswin:
  PCI: eswin: Add ESWIN PCIe Root Complex driver
  dt-bindings: PCI: eswin: Add ESWIN PCIe Root Complex

# Conflicts:
#	drivers/pci/controller/dwc/Kconfig
#	drivers/pci/controller/dwc/Makefile

- Add Andes QiLai SoC PCIe host driver support (Randolph Lin)

* pci/controller/dwc-andes-qilai:
  PCI: qilai: Add Andes QiLai SoC PCIe host driver support
  dt-bindings: PCI: Add Andes QiLai PCIe support

# Conflicts:
#	drivers/pci/controller/dwc/Makefile

- Continue with system suspend even if an Endpoint doesn't respond with
  PME_TO_Ack message (Manivannan Sadhasivam)

- Remove the Baikal-T1 controller driver since it never quite became usable
  (Andy Shevchenko)

- Set Endpoint MSI-X Table Size in the correct function of a multi-function
  device when configuring MSI-X, not in Function 0 (Aksh Garg)

- Set Max Link Width and Max Link Speed for all functions of a
  multi-function device, not just Function 0 (Aksh Garg)

- Clean up in the dw_pcie_resume_noirq() error path (Manivannan Sadhasivam)

- Expose PCIe event counters in groups 5-7 in debugfs (Hans Zhang)

- Fix type mismatch for kstrtou32_from_user() in debugfs write functions
  (Hans Zhang)

* pci/controller/dwc:
  PCI: dwc: Fix type mismatch for kstrtou32_from_user() return value
  PCI: dwc: Expose PCIe event counters for groups 5 to 7 over debugfs
  PCI: dwc: Perform cleanup in the error path of dw_pcie_resume_noirq()
  PCI: dwc: ep: Mirror the max link width and speed fields to all functions
  PCI: dwc: ep: Fix MSI-X Table Size configuration in dw_pcie_ep_set_msix()
  PCI: dwc: Remove not-going-to-be-supported code for Baikal SoC
  PCI: dwc: Proceed with system suspend even if the endpoint doesn't respond with PME_TO_Ack message

Tegra supports PCIe core clock monitoring for any rate changes that may be
happening because of the link speed changes. This is useful in tracking
any changes in the core clock that are not initiated by the software.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com>
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Tested-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
Link: https://patch.msgid.link/20260324191000.1095768-7-mmaddireddy@nvidia.com

Add bindings support for PCIe endpoint controllers in i.MX94 and i.MX943
SoCs with fallback to the i.MX95 SoC.

Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://patch.msgid.link/20260324023036.784466-3-hongxing.zhu@nxp.com

Commit 1352f58d7c8d ("dt-bindings: PCI: pci-imx6: Add external reference
clock input") that added reference clock to the binding was incomplete.

The constraints for "clocks" and "clock-names" still enforce an incorrect
number of items. Update maxItems for both properties to 6 to match the
actual hardware configuration.

Fixes: 1352f58d7c8d ("dt-bindings: PCI: pci-imx6: Add external reference clock input")
Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com>
[mani: commit log]
Signed-off-by: Manivannan Sadhasivam <mani@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260324023036.784466-2-hongxing.zhu@nxp.com

The six PCIe controllers found on Tegra264 are of two types: one is used
for the internal GPU and therefore is not connected to a UPHY and the
remaining five controllers are typically routed to a PCI slot and have
additional controls for the physical link.

While these controllers can be switched into endpoint mode, this binding
describes the root complex mode only.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>