<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/Documentation/devicetree/bindings/nvmem, branch v4.13</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>nvmem: rockchip-efuse: amend compatible rk322x-efuse to rk3228-efuse</title>
<updated>2017-07-17T14:15:57+00:00</updated>
<author>
<name>Frank Wang</name>
<email>frank.wang@rock-chips.com</email>
</author>
<published>2017-07-14T08:38:43+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=d6e4bd1b52bf35e7fc14b52be7dbe784896398e3'/>
<id>d6e4bd1b52bf35e7fc14b52be7dbe784896398e3</id>
<content type='text'>
As the comments from Heiko Stuebner &lt;heiko@sntech.de&gt; that compatible
should not contain any placeholders, this patch fix it for rk3228 SoC.

Note that this is a fix for v4.13, due to fixing the current non-standard
binding name that should not become part of an official kernel release.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
As the comments from Heiko Stuebner &lt;heiko@sntech.de&gt; that compatible
should not contain any placeholders, this patch fix it for rk3228 SoC.

Note that this is a fix for v4.13, due to fixing the current non-standard
binding name that should not become part of an official kernel release.

Signed-off-by: Frank Wang &lt;frank.wang@rock-chips.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nvmem: rockchip-efuse: add support for rk322x-efuse</title>
<updated>2017-06-09T10:08:27+00:00</updated>
<author>
<name>Finley Xiao</name>
<email>finley.xiao@rock-chips.com</email>
</author>
<published>2017-06-09T09:59:10+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=820de1fb69f16a4307e4b5d4adf6e9246a680655'/>
<id>820de1fb69f16a4307e4b5d4adf6e9246a680655</id>
<content type='text'>
This adds the necessary data for handling eFuse on the rk322x.

Signed-off-by: Finley Xiao &lt;finley.xiao@rock-chips.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
This adds the necessary data for handling eFuse on the rk322x.

Signed-off-by: Finley Xiao &lt;finley.xiao@rock-chips.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nvmem: imx-ocotp: add write support</title>
<updated>2017-04-08T15:51:48+00:00</updated>
<author>
<name>Richard Leitner</name>
<email>richard.leitner@skidata.com</email>
</author>
<published>2017-03-31T12:44:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=0642bac7da4240912c3e923a7d1c47af3dd89b9d'/>
<id>0642bac7da4240912c3e923a7d1c47af3dd89b9d</id>
<content type='text'>
Implement write routine for OCOTP controller found in i.MX6 SoC's.
Furthermore add locking to the read function to prevent race conditions.
The write routine code is based on the fsl_otp driver from Freescale.

Signed-off-by: Richard Leitner &lt;richard.leitner@skidata.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Implement write routine for OCOTP controller found in i.MX6 SoC's.
Furthermore add locking to the read function to prevent race conditions.
The write routine code is based on the fsl_otp driver from Freescale.

Signed-off-by: Richard Leitner &lt;richard.leitner@skidata.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: imx-ocotp: add compatible string for i.MX7D/S</title>
<updated>2017-04-08T15:51:48+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2017-03-31T12:44:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=8bb79e85cc4ad859bda3cd1dda0abc505bafcc29'/>
<id>8bb79e85cc4ad859bda3cd1dda0abc505bafcc29</id>
<content type='text'>
Add compatible string for i.MX7D/S

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Shawn Guo &lt;shawnguo@kernel.org&gt;
Cc: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add compatible string for i.MX7D/S

Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Cc: Shawn Guo &lt;shawnguo@kernel.org&gt;
Cc: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: nvmem: Add i.MX IIM binding doc</title>
<updated>2017-04-08T15:51:48+00:00</updated>
<author>
<name>Sascha Hauer</name>
<email>s.hauer@pengutronix.de</email>
</author>
<published>2017-03-31T12:44:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=40bbb60cecc0ff145f56b69af08b340acd8fba9e'/>
<id>40bbb60cecc0ff145f56b69af08b340acd8fba9e</id>
<content type='text'>
The IIM is part of the i.MX device trees for long already, add a binding
document for it.

Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The IIM is part of the i.MX device trees for long already, add a binding
document for it.

Signed-off-by: Sascha Hauer &lt;s.hauer@pengutronix.de&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nvmem: sunxi-sid: add support for H3's SID controller</title>
<updated>2017-04-08T15:51:48+00:00</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.xyz</email>
</author>
<published>2017-03-31T12:44:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1a9636426b9f994d57dfe5a64e3f4644747a2e95'/>
<id>1a9636426b9f994d57dfe5a64e3f4644747a2e95</id>
<content type='text'>
The H3 SoC have a bigger SID controller, which has its direct read
address at 0x200 position in the SID block, not 0x0.

Also, H3 SID controller has some silicon bug that makes the direct read
value wrong at cold boot, add code to workaround the bug. (This bug has
already been fixed on A64 and later SoCs)

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.xyz&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The H3 SoC have a bigger SID controller, which has its direct read
address at 0x200 position in the SID block, not 0x0.

Also, H3 SID controller has some silicon bug that makes the direct read
value wrong at cold boot, add code to workaround the bug. (This bug has
already been fixed on A64 and later SoCs)

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.xyz&gt;
Acked-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>devicetree: bindings: nvmem: Add compatible string for imx6ul</title>
<updated>2017-01-25T10:49:39+00:00</updated>
<author>
<name>Bai Ping</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2017-01-22T23:02:37+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1e928fff9a7444cbfbbb2420eb8cec79bfa53c6f'/>
<id>1e928fff9a7444cbfbbb2420eb8cec79bfa53c6f</id>
<content type='text'>
Add new compatible string for i.MX6UL SOC.

Signed-off-by: Bai Ping &lt;ping.bai@nxp.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add new compatible string for i.MX6UL SOC.

Signed-off-by: Bai Ping &lt;ping.bai@nxp.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: Document Broadcom OTP controller driver</title>
<updated>2016-11-10T14:34:55+00:00</updated>
<author>
<name>Jonathan Richardson</name>
<email>jonathar@broadcom.com</email>
</author>
<published>2016-10-31T14:45:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=dff20aa1a076ae5aab2170dd541fe52d729fb3f4'/>
<id>dff20aa1a076ae5aab2170dd541fe52d729fb3f4</id>
<content type='text'>
Reviewed-by: Ray Jui &lt;ray.jui@broadcom.com&gt;
Tested-by: Jonathan Richardson &lt;jonathan.richardson@broadcom.com&gt;
Signed-off-by: Scott Branden &lt;scott.branden@broadcom.com&gt;
Signed-off-by: Oza Pawandeep &lt;oza@broadcom.com&gt;
Signed-off-by: Jonathan Richardson &lt;jonathan.richardson@broadcom.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Reviewed-by: Ray Jui &lt;ray.jui@broadcom.com&gt;
Tested-by: Jonathan Richardson &lt;jonathan.richardson@broadcom.com&gt;
Signed-off-by: Scott Branden &lt;scott.branden@broadcom.com&gt;
Signed-off-by: Oza Pawandeep &lt;oza@broadcom.com&gt;
Signed-off-by: Jonathan Richardson &lt;jonathan.richardson@broadcom.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>nvmem: dt: document lpc1850 OTP binding</title>
<updated>2016-11-10T14:34:55+00:00</updated>
<author>
<name>Joachim Eastwood</name>
<email>manabian@gmail.com</email>
</author>
<published>2016-10-31T14:45:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b16ebc017ebf52a81e5e88743ccd68fc25e99ba9'/>
<id>b16ebc017ebf52a81e5e88743ccd68fc25e99ba9</id>
<content type='text'>
Documenation for the LPC18xx/43xx OTP memory bindings.

Signed-off-by: Joachim Eastwood &lt;manabian@gmail.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Documenation for the LPC18xx/43xx OTP memory bindings.

Signed-off-by: Joachim Eastwood &lt;manabian@gmail.com&gt;
Signed-off-by: Srinivas Kandagatla &lt;srinivas.kandagatla@linaro.org&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2016-10-08T04:34:49+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2016-10-08T04:34:49+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=c913fc4146ba7c280e074558d0a461e5c6f07c8a'/>
<id>c913fc4146ba7c280e074558d0a461e5c6f07c8a</id>
<content type='text'>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

   - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
     automotive SoC similar to the ⅹ8a7795 chip we already support, but
     the dts changes rely on a clock driver change that has been merged
     for v4.9 through the clk tree.

   - The Amlogic meson-gxbb (S905) platform gains support for a few
     drivers merged through our tree, in particular the network and usb
     driver changes are required and included here, and also the clk
     tree changes.

   - The Allwinner platforms have seen a large-scale change to their clk
     drivers and the dts file updates must come after that. This
     includes the newly added Nextthing GR8 platform, which is derived
     from sun5i/A13.

   - Some integrator (arm32) changes rely on clk driver changes.

   - A single patch for lpc32xx has no such dependency but wasn't added
     until just before the merge window"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  ARM: dts: lpc32xx: add device node for IRAM on-chip memory
  ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
  ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
  ARM: dts: sun8i: add pinmux for UART1 at PG
  dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
  dts: sun8i-h3: add pinmux definitions for I2C0-2
  dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
  dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
  dts: sun8i-h3: add pinmux definitions for UART2-3
  ARM: dts: sun9i: a80-optimus: Disable EHCI1
  ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
  ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
  ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull ARM SoC late DT updates from Arnd Bergmann:
 "These updates have been kept in a separate branch mostly because they
  rely on updates to the respective clk drivers to keep the shared
  header files in sync.

   - The Renesas r8a7796 (R-Car M3-W) platform gets added, this is an
     automotive SoC similar to the ⅹ8a7795 chip we already support, but
     the dts changes rely on a clock driver change that has been merged
     for v4.9 through the clk tree.

   - The Amlogic meson-gxbb (S905) platform gains support for a few
     drivers merged through our tree, in particular the network and usb
     driver changes are required and included here, and also the clk
     tree changes.

   - The Allwinner platforms have seen a large-scale change to their clk
     drivers and the dts file updates must come after that. This
     includes the newly added Nextthing GR8 platform, which is derived
     from sun5i/A13.

   - Some integrator (arm32) changes rely on clk driver changes.

   - A single patch for lpc32xx has no such dependency but wasn't added
     until just before the merge window"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (99 commits)
  ARM: dts: lpc32xx: add device node for IRAM on-chip memory
  ARM: dts: sun8i: Add accelerometer to polaroid-mid2407pxe03
  ARM: dts: sun8i: enable UART1 for iNet D978 Rev2 board
  ARM: dts: sun8i: add pinmux for UART1 at PG
  dts: sun8i-h3: add I2C0-2 peripherals to H3 SOC
  dts: sun8i-h3: add pinmux definitions for I2C0-2
  dts: sun8i-h3: associate exposed UARTs on Orange Pi Boards
  dts: sun8i-h3: split off RTS/CTS for UART1 in seperate pinmux
  dts: sun8i-h3: add pinmux definitions for UART2-3
  ARM: dts: sun9i: a80-optimus: Disable EHCI1
  ARM: dts: sun9i: cubieboard4: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: a80-optimus: Add AXP806 PMIC device node and regulators
  ARM: dts: sun9i: cubieboard4: Declare AXP809 SW regulator as unused
  ARM: dts: sun9i: a80-optimus: Declare AXP809 SW regulator as unused
  ARM: dts: sun8i: Add touchscreen node for sun8i-a33-ga10h
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2809pxe04
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-polaroid-mid2407pxe03
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-inet86dz
  ARM: dts: sun8i: Add touchscreen node for sun8i-a23-gt90h
  ARM64: dts: meson-gxbb-vega-s95: Enable USB Nodes
  ...
</pre>
</div>
</content>
</entry>
</feed>
