linux.git/Documentation/devicetree/bindings/net, branch v3.19 Linux kernel source tree net: davinci_emac: Add support for emac on dm816x 2015-01-16T06:00:03+00:00 Tony Lindgren tony@atomide.com 2015-01-15T22:45:14+00:00 de3900833ee635d5658415fea9c8c4e13507d777 On dm816x we have two emac controllers with separate memory areas. Cc: Brian Hutchinson <b.hutchman@gmail.com> Cc: Felipe Balbi <balbi@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
On dm816x we have two emac controllers with separate memory
areas.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
dt/bindings: add clock-select function property to micrel phy binding 2014-11-21T19:08:57+00:00 Johan Hovold johan@kernel.org 2014-11-19T11:59:21+00:00 c3a8e1eddd6c140fbaaf957f7da8f2175f79623d Add "micrel,rmii-reference-clock-select-25-mhz" to Micrel ethernet PHY binding documentation. This property is needed to properly describe some revisions of Micrel PHYs which has the function of this configuration bit inverted so that setting it enables 25 MHz rather than 50 MHz clock mode. Note that a clock reference ("rmii-ref") is still needed to actually select either mode. Cc: devicetree@vger.kernel.org Signed-off-by: Johan Hovold <johan@kernel.org> Acked-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: David S. Miller <davem@davemloft.net> 
Add "micrel,rmii-reference-clock-select-25-mhz" to Micrel ethernet PHY
binding documentation.

This property is needed to properly describe some revisions of Micrel
PHYs which has the function of this configuration bit inverted so that
setting it enables 25 MHz rather than 50 MHz clock mode.

Note that a clock reference ("rmii-ref") is still needed to actually
select either mode.

Cc: devicetree@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: David S. Miller <davem@davemloft.net>
dt/bindings: reformat micrel eth-phy documentation 2014-11-21T19:08:57+00:00 Johan Hovold johan@kernel.org 2014-11-19T11:59:20+00:00 6d01329444725a5c17cf75ba6c5c0c5e42843613 Reduce indentation of Micrel PHY binding documentations somewhat. Also fix "reference input clock" typo while at it. Cc: devicetree@vger.kernel.org Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net> 
Reduce indentation of Micrel PHY binding documentations somewhat.

Also fix "reference input clock" typo while at it.

Cc: devicetree@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: micrel: add support for clock-mode select to KSZ8081/KSZ8091 2014-11-21T19:08:56+00:00 Johan Hovold johan@kernel.org 2014-11-19T11:59:19+00:00 86dc1342bcbb1905b2ac9653a559b303f62bd728 Micrel KSZ8081 and KSZ8091 PHYs have the RMII Reference Clock Select bit, which is used to select 25 or 50 MHz clock mode. Note that on some revisions of the PHY (e.g. KSZ8081RND) the function of this bit is inverted so that setting it enables 25 rather than 50 MHz mode. Add a new device-tree property "micrel,rmii-reference-clock-select-25-mhz" to describe this. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net> 
Micrel KSZ8081 and KSZ8091 PHYs have the RMII Reference Clock Select
bit, which is used to select 25 or 50 MHz clock mode.

Note that on some revisions of the PHY (e.g. KSZ8081RND) the function of
this bit is inverted so that setting it enables 25 rather than 50 MHz
mode. Add a new device-tree property
"micrel,rmii-reference-clock-select-25-mhz" to describe this.

Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: can: c_can: Add support for TI am4372 DCAN 2014-11-17T14:32:10+00:00 Roger Quadros rogerq@ti.com 2014-11-17T12:09:03+00:00 f2bf2589834faec7af8c02c3949c90788d21b790 AM4372 SoC has 2 DCAN modules. Add compatible id and raminit driver data for it. The driver data is same as AM3352 but this gives us flexibility to add AM4372 specific quirks if required later. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> 
AM4372 SoC has 2 DCAN modules. Add compatible id and
raminit driver data for it. The driver data is same as AM3352
but this gives us flexibility to add AM4372 specific quirks
if required later.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
can: c_can: Add support for TI am3352 DCAN 2014-11-17T11:19:27+00:00 Roger Quadros rogerq@ti.com 2014-11-07T14:49:22+00:00 c71d0b31bf71b84ad566292ea2412755da7934b2 AM3352 SoC has 2 DCAN modules. Add compatible id and raminit driver data for am3352 DCAN. Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Wolfram Sang <wsa@the-dreams.de> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> 
AM3352 SoC has 2 DCAN modules. Add compatible id and
raminit driver data for am3352 DCAN.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
can: c_can: Add support for TI DRA7 DCAN 2014-11-17T11:19:27+00:00 Roger Quadros rogerq@ti.com 2014-11-07T14:49:21+00:00 0f4da3a8da5fe3a079b1adf613d121a0fafd63f1 DRA7 SoC has 2 CAN IPs. Provide compatible IDs and RAMINIT register data for both. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> 
DRA7 SoC has 2 CAN IPs. Provide compatible IDs and RAMINIT
register data for both.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
can: c_can: Add syscon/regmap RAMINIT mechanism 2014-11-17T11:19:27+00:00 Roger Quadros rogerq@ti.com 2014-11-14T15:37:39+00:00 3ff9027ca6b00e194d2eae353febf7233cfcc1ea Some TI SoCs like DRA7 have a RAMINIT register specification different from the other AMxx SoCs and as expected by the existing driver. To add more insanity, this register is shared with other IPs like DSS, PCIe and PWM. Provides a more generic mechanism to specify the RAMINIT register location and START/DONE bit position and use the syscon/regmap framework to access the register. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de> 
Some TI SoCs like DRA7 have a RAMINIT register specification
different from the other AMxx SoCs and as expected by the
existing driver.

To add more insanity, this register is shared with other
IPs like DSS, PCIe and PWM.

Provides a more generic mechanism to specify the RAMINIT
register location and START/DONE bit position and use the
syscon/regmap framework to access the register.

Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
net: sh_eth: Add r8a7793 support 2014-11-13T20:03:53+00:00 Hisashi Nakamura hisashi.nakamura.ak@renesas.com 2014-11-13T06:59:07+00:00 9488e1e5b319751c71eebfd49027bf9e2377f38c The device tree probing for R-Car M2N (r8a7793) is added. Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com> Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com> Signed-off-by: David S. Miller <davem@davemloft.net> 
The device tree probing for R-Car M2N (r8a7793) is added.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
net: phy: micrel: enable led-mode for KSZ8081/KSZ8091 2014-11-12T18:55:37+00:00 Johan Hovold johan@kernel.org 2014-11-11T19:00:15+00:00 7b52314cc44569f56aa07abdbe43e6ccfcef9478 Enable led-mode configuration for KSZ8081 and KSZ8091. Signed-off-by: Johan Hovold <johan@kernel.org> Signed-off-by: David S. Miller <davem@davemloft.net> 
Enable led-mode configuration for KSZ8081 and KSZ8091.

Signed-off-by: Johan Hovold <johan@kernel.org>
Signed-off-by: David S. Miller <davem@davemloft.net>