linux.git/Documentation/devicetree/bindings/memory-controllers, branch v5.11

Merge tag 'memory-controller-drv-tegra-5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

2020-12-08T23:40:02+00:00

Memory controller drivers for v5.11 - Tegra SoC, part two

Continuation of work on Tegra SoC memory controllers towards adding
interconnect support and integration with devfreq.

This brings few more patches including one which removes/fixes annoying
warning if the DTS patches get applied.  This is expected and only
informs that new features of Tegra memory controller drivers will not be
enabled however the warning itself could look worrying.

* tag 'memory-controller-drv-tegra-5.11-3' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl:
  memory: tegra30: Support interconnect framework
  memory: tegra20: Support hardware versioning and clean up OPP table initialization
  dt-bindings: memory: tegra20-emc: Document opp-supported-hw property

Link: https://lore.kernel.org/r/20201207075758.5501-2-krzk@kernel.org
Signed-off-by: Arnd Bergmann

dt-bindings: memory: tegra20-emc: Document opp-supported-hw property

2020-12-05T13:53:33+00:00

Document opp-supported-hw property, which is not strictly necessary to
have on Tegra20, but it's very convenient to have because all other SoC
core devices will use hardware versioning, and thus, it's good to maintain
the consistency.

Signed-off-by: Dmitry Osipenko 
Acked-by: Thierry Reding 
Link: https://lore.kernel.org/r/20201203192439.16177-2-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

Merge tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl into arm/drivers

2020-11-26T21:05:15+00:00

Memory controller drivers for v5.11 - Tegra SoC

There is a bigger work from Dmitry Osipenko around Tegra SoC memory
controller drivers, mostly towards adding interconnect support and
integration with devfreq.  This work touches all Tegra memory controller
drivers and also few other SoC-related parts.  It's not yet finished but
the intermediate stage seems ready to merge.

Beside that Tegra 210 memory controller got few fixes and received new
swgroups (work of Nicolin Chen).

* tag 'memory-controller-drv-tegra-5.11-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux-mem-ctrl: (38 commits)
  memory: tegra30-emc: Remove unnecessary of_node_put in tegra_emc_probe
  memory: tegra: Complete tegra210_swgroups
  memory: tegra30-emc: Continue probing if timings are missing in device-tree
  memory: tegra30-emc: Make driver modular
  memory: tegra30: Add FIFO sizes to memory clients
  memory: tegra20-emc: Add devfreq support
  memory: tegra20-emc: Remove IRQ number from error message
  memory: tegra20-emc: Factor out clk initialization
  memory: tegra20-emc: Use dev_pm_opp_set_clkname()
  memory: tegra: Correct stub of devm_tegra_memory_controller_get()
  memory: tegra20: Support interconnect framework
  memory: tegra20-emc: Continue probing if timings are missing in device-tree
  memory: tegra20-emc: Make driver modular
  memory: tegra-mc: Add interconnect framework
  memory: tegra: Add missing latency allowness entry for Page Table Cache
  memory: tegra: Remove superfluous error messages around platform_get_irq()
  memory: tegra: Use devm_platform_ioremap_resource()
  memory: tegra: Add and use devm_tegra_memory_controller_get()
  dt-bindings: host1x: Document new interconnect properties
  dt-bindings: tegra30-actmon: Document OPP and interconnect properties
  ...

Link: https://lore.kernel.org/r/20201126191241.23302-1-krzk@kernel.org
Signed-off-by: Arnd Bergmann

dt-bindings: memory: tegra124: emc: Document OPP table and voltage regulator

2020-11-06T18:37:19+00:00

Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.

Signed-off-by: Dmitry Osipenko 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-15-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra124: emc: Document new interconnect property

2020-11-06T18:33:58+00:00

External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.

Signed-off-by: Dmitry Osipenko 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-14-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra124: mc: Document new interconnect property

2020-11-06T18:33:39+00:00

Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.

Signed-off-by: Dmitry Osipenko 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-13-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra30: emc: Document OPP table and voltage regulator

2020-11-06T18:32:10+00:00

Document new OPP table and voltage regulator properties which are needed
for supporting dynamic voltage-frequency scaling of the memory controller.
Some boards may have a fixed core voltage regulator, hence it's optional
because frequency scaling still may be desired.

Signed-off-by: Dmitry Osipenko 
Reviewed-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-12-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra30: emc: Document new interconnect property

2020-11-06T18:31:45+00:00

External memory controller is interconnected with memory controller and
with external memory. Document new interconnect property which turns
External Memory Controller into interconnect provider.

Signed-off-by: Dmitry Osipenko 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-11-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra30: mc: Document new interconnect property

2020-11-06T18:31:25+00:00

Memory controller is interconnected with memory clients and with the
External Memory Controller. Document new interconnect property which
turns memory controller into interconnect provider.

Signed-off-by: Dmitry Osipenko 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-10-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski

dt-bindings: memory: tegra20: emc: Document OPP table and voltage regulator

2020-11-06T18:30:59+00:00

The SoC core voltage can't be changed without taking into account the
clock rate of External Memory Controller. Document OPP table that will
be used for dynamic voltage frequency scaling, taking into account EMC
voltage requirement. Document optional core voltage regulator, which is
optional because some boards may have a fixed core regulator and still
frequency scaling may be desired to have.

Signed-off-by: Dmitry Osipenko 
Acked-by: Rob Herring 
Link: https://lore.kernel.org/r/20201104164923.21238-9-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski