linux.git/Documentation/devicetree/bindings/interconnect, branch v6.17 Linux kernel source tree Merge tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2025-07-29T18:04:52+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-07-29T18:04:52+00:00 115e74a29b530d121891238e9551c4bcdf7b04b5 Pull SoC devicetree updates from Arnd Bergmann: "There are a few new variants of existing chips: - mt6572 is an older mobile phone chip from mediatek that was extremely popular a decade ago but never got upstreamed until now - exynos2200 is a recent high-end mobile phone chip used in a few Samsung phones like the Galaxy S22 - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M (R8A779H0) and used in automotive applications - Tegra264 is a new chip from NVIDIA, but support is fairly minimal for now, and not much information is public about it There are five more chips in a separate branch, as those are new chip families that I merged along with the necessary infrastructure. New board support is not that exciting, with a total of 33 newly added machines here: - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo sg2042 - Six 32-bit industrial boards based on stm32, imx6 and am33 chips, plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and imx95 - Two newly added ASPEED BMC based motherboards, and one that got removed - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit msm8976 SoCs - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1 - A set-top box based on Amlogic meson-gxm Updates for existing machines are spread over all the above families. One notable change here is support for the RP1 I/O chip used in Raspberry Pi 5" * tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits) riscv: dts: sophgo: fix mdio node name for CV180X riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings riscv: dts: sophgo: add ethernet GMAC device for sg2042 riscv: dts: sophgo: Enable ethernet device for Huashan Pi riscv: dts: sophgo: Add mdio multiplexer device for cv18xx riscv: dts: sophgo: Add ethernet device for cv18xx riscv: dts: sophgo: sg2044: add pmu configuration riscv: dts: sophgo: sg2044: add ziccrse extension riscv: dts: sophgo: add zfh for sg2042 riscv: dts: sophgo: add ziccrse for sg2042 riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree riscv: dts: sophgo: sg2044: add PCIe device support for SG2044 riscv: dts: sophgo: sg2044: add MSI device support for SG2044 riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000 riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property ... 
Pull SoC devicetree updates from Arnd Bergmann:
 "There are a few new variants of existing chips:

   - mt6572 is an older mobile phone chip from mediatek that was
     extremely popular a decade ago but never got upstreamed until now

   - exynos2200 is a recent high-end mobile phone chip used in a few
     Samsung phones like the Galaxy S22

   - Renesas R-Car V4M-7 (R8A779H2) is an updated version of R-Car V4M
     (R8A779H0) and used in automotive applications

   - Tegra264 is a new chip from NVIDIA, but support is fairly minimal
     for now, and not much information is public about it

  There are five more chips in a separate branch, as those are new chip
  families that I merged along with the necessary infrastructure.

  New board support is not that exciting, with a total of 33 newly added
  machines here:

   - Evaluation platforms for the chips above, plus TI am62d2 and Sophgo
     sg2042

   - Six 32-bit industrial boards based on stm32, imx6 and am33 chips,
     plus eight 64-bit rockchips rk33xx/rk35xx, am62d2, t527, imx8 and
     imx95

   - Two newly added ASPEED BMC based motherboards, and one that got
     removed

   - Phones and Tablets based on 32-bit mt6572, tegra30 and 64-bit
     msm8976 SoCs

   - Three Laptops based on Mediatek mt8186 and Qualcomm Snapdragon X1

   - A set-top box based on Amlogic meson-gxm

  Updates for existing machines are spread over all the above families.
  One notable change here is support for the RP1 I/O chip used in
  Raspberry Pi 5"

* tag 'soc-dt-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (606 commits)
  riscv: dts: sophgo: fix mdio node name for CV180X
  riscv: dts: sophgo: sophgo-srd3-10: reserve uart0 device
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V2.0 board device tree
  riscv: dts: sophgo: add Sophgo SG2042_EVB_V1.X board device tree
  dt-bindings: riscv: add Sophgo SG2042_EVB_V1.X/V2.0 bindings
  riscv: dts: sophgo: add ethernet GMAC device for sg2042
  riscv: dts: sophgo: Enable ethernet device for Huashan Pi
  riscv: dts: sophgo: Add mdio multiplexer device for cv18xx
  riscv: dts: sophgo: Add ethernet device for cv18xx
  riscv: dts: sophgo: sg2044: add pmu configuration
  riscv: dts: sophgo: sg2044: add ziccrse extension
  riscv: dts: sophgo: add zfh for sg2042
  riscv: dts: sophgo: add ziccrse for sg2042
  riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  riscv: dts: sophgo: sg2044: add PCIe device support for SG2044
  riscv: dts: sophgo: sg2044: add MSI device support for SG2044
  riscv: dts: sophgo: add reset configuration for Sophgo CV1800 series SoC
  riscv: dts: sophgo: add reset generator for Sophgo CV1800 series SoC
  dt-bindings: soc: sophgo: Move SoCs/boards from riscv into soc, add SG2000
  riscv: dts: sophgo: sg2044: Add missing riscv,cbop-block-size property
  ...
Merge branch 'icc-milos' into icc-next 2025-07-22T11:41:12+00:00 Georgi Djakov djakov@kernel.org 2025-07-22T15:18:41+00:00 ca652cf0c2612add5d3c9283bbc742dabc704a77 Add documentation and driver for the interconnect on the Milos SoC. * icc-milos dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC interconnect: qcom: Add Milos interconnect provider driver Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-0-c446203c3b3a@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
Add documentation and driver for the interconnect on the Milos SoC.

* icc-milos
  dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC
  interconnect: qcom: Add Milos interconnect provider driver

Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-0-c446203c3b3a@fairphone.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: document the RPMh Network-On-Chip Interconnect in Qualcomm Milos SoC 2025-07-21T16:41:07+00:00 Luca Weiss luca.weiss@fairphone.com 2025-07-09T13:14:49+00:00 0f29e33fbadd7517b96f3f3e86220215d99875cb Document the RPMh Network-On-Chip Interconnect of the Milos (e.g. SM7635) SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-1-c446203c3b3a@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
Document the RPMh Network-On-Chip Interconnect of the Milos (e.g.
SM7635) SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-1-c446203c3b3a@fairphone.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: qcom,msm8998-bwmon: Allow 'nonposted-mmio' 2025-07-18T14:54:58+00:00 Konrad Dybcio konrad.dybcio@oss.qualcomm.com 2025-07-16T12:25:46+00:00 a234cffd04bc06386b18976de5b691b23bcf68a4 One of the BWMON instances on SM8750 requires that its MMIO space is mapped specifically with the nE memory attribute. Allow the nonposted-mmio property which instructs the OS to do so. Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250716-8750_cpubwmon-v4-1-12212098e90f@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
One of the BWMON instances on SM8750 requires that its MMIO space is
mapped specifically with the nE memory attribute.

Allow the nonposted-mmio property which instructs the OS to do so.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250716-8750_cpubwmon-v4-1-12212098e90f@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: Add EPSS L3 compatible for QCS8300 SoC 2025-07-18T14:54:58+00:00 Raviteja Laggyshetty raviteja.laggyshetty@oss.qualcomm.com 2025-07-11T10:25:38+00:00 a95571d8ffe2fa92bcc2af22a853170340ae1e9c Add Epoch Subsystem (EPSS) L3 interconnect provider binding for QCS8300 SoC. As the EPSS hardware in QCS8300 and SA8775P are same, added a family-level compatible for SA877P SoC. This shared fallback compatible allows grouping of SoCs with similar hardware, reducing the need to explicitly list each variant in the driver match table. Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250711102540.143-2-raviteja.laggyshetty@oss.qualcomm.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding for
QCS8300 SoC. As the EPSS hardware in QCS8300 and SA8775P are same,
added a family-level compatible for SA877P SoC. This shared fallback
compatible allows grouping of SoCs with similar hardware, reducing
the need to explicitly list each variant in the driver match table.

Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250711102540.143-2-raviteja.laggyshetty@oss.qualcomm.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: qcom: Remove double colon from description 2025-07-18T14:54:58+00:00 Luca Weiss luca.weiss@fairphone.com 2025-07-17T06:54:45+00:00 a8d7161d1dba668d814e66b28aef235341d7b1ed No double colon is necessary in the description. Fix it for all bindings so future bindings won't have the same copy-paste mistake. Reported-by: Rob Herring <robh@kernel.org> Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/ Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-2-c04abc180fcd@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
No double colon is necessary in the description. Fix it for all bindings
so future bindings won't have the same copy-paste mistake.

Reported-by: Rob Herring <robh@kernel.org>
Closes: https://lore.kernel.org/lkml/20250625150458.GA1182597-robh@kernel.org/
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250717-bindings-double-colon-v1-2-c04abc180fcd@fairphone.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: add mt7988-cci compatible 2025-07-07T08:57:03+00:00 Frank Wunderlich frank-w@public-files.de 2025-07-06T13:22:02+00:00 bd9e0f5d90959d2d07986084fbd58042b62aa549 Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback which is taken by driver. Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Acked-by: Georgi Djakov <djakov@kernel.org> Link: https://lore.kernel.org/r/20250706132213.20412-8-linux@fw-web.de Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 
Add compatible for Mediatek MT7988 SoC with mediatek,mt8183-cci fallback
which is taken by driver.

Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Georgi Djakov <djakov@kernel.org>
Link: https://lore.kernel.org/r/20250706132213.20412-8-linux@fw-web.de
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Merge branch 'icc-sa8775p' into icc-next 2025-05-19T14:09:50+00:00 Georgi Djakov djakov@kernel.org 2025-05-19T14:09:50+00:00 5fed7fe33c2cd7104fc87b7bc699a7be892befa2 Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs. Current interconnect framework is based on static IDs for creating node and registering with framework. This becomes a limitation for topologies where there are multiple instances of same interconnect provider. Modified interconnect framework APIs to create and link icc node with dynamic IDs, this will help to overcome the dependency on static IDs. * icc-sa8775p dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P interconnect: core: Add dynamic id allocation support interconnect: qcom: Add multidev EPSS L3 support interconnect: qcom: icc-rpmh: Add dynamic icc node id support interconnect: qcom: sa8775p: Add dynamic icc node id support Link: https://lore.kernel.org/r/20250415095343.32125-1-quic_rlaggysh@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs.

Current interconnect framework is based on static IDs for creating node
and registering with framework. This becomes a limitation for topologies
where there are multiple instances of same interconnect provider.
Modified interconnect framework APIs to create and link icc node with
dynamic IDs, this will help to overcome the dependency on static IDs.

* icc-sa8775p
  dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
  interconnect: core: Add dynamic id allocation support
  interconnect: qcom: Add multidev EPSS L3 support
  interconnect: qcom: icc-rpmh: Add dynamic icc node id support
  interconnect: qcom: sa8775p: Add dynamic icc node id support

Link: https://lore.kernel.org/r/20250415095343.32125-1-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: Correct indentation and style in DTS example 2025-04-28T14:46:35+00:00 Krzysztof Kozlowski krzysztof.kozlowski@linaro.org 2025-03-24T12:53:02+00:00 af73692e7b486497b8983d7cabbcd5e4dcf5cb98 DTS example in the bindings should be indented with 2- or 4-spaces and aligned with opening '- |', so correct any differences like 3-spaces or mixtures 2- and 4-spaces in one binding. While re-indenting, drop unused labels. No functional changes here, but saves some comments during reviews of new patches built on existing code. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org> Link: https://lore.kernel.org/r/20250324125302.82167-1-krzysztof.kozlowski@linaro.org Signed-off-by: Georgi Djakov <djakov@kernel.org> 
DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.  While re-indenting, drop
unused labels.

No functional changes here, but saves some comments during reviews of
new patches built on existing code.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250324125302.82167-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P 2025-04-15T11:13:30+00:00 Raviteja Laggyshetty quic_rlaggysh@quicinc.com 2025-04-15T09:53:37+00:00 289198fb51420def0f6fa88ed5808d0d38120ad0 Add Epoch Subsystem (EPSS) L3 interconnect provider binding on SA8775P SoCs. The L3 instance on the SA8775P SoC is similar to those on SoCs like SM8250 and SC7280. These SoCs use the PERF register instead of L3_REG for programming the performance level, which is managed in the data associated with the target-specific compatibles. Since the hardware remains the same across all EPSS-supporting SoCs, the generic compatible is retained for all SoCs. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com> Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com Signed-off-by: Georgi Djakov <djakov@kernel.org> 
Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
The L3 instance on the SA8775P SoC is similar to those on SoCs
like SM8250 and SC7280. These SoCs use the PERF register instead
of L3_REG for programming the performance level, which is managed
in the data associated with the target-specific compatibles.
Since the hardware remains the same across all EPSS-supporting SoCs,
the generic compatible is retained for all SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>