Add Epoch Subsystem (EPSS) L3 provider support on SA8775P SoCs.

Current interconnect framework is based on static IDs for creating node
and registering with framework. This becomes a limitation for topologies
where there are multiple instances of same interconnect provider.
Modified interconnect framework APIs to create and link icc node with
dynamic IDs, this will help to overcome the dependency on static IDs.

* icc-sa8775p
  dt-bindings: interconnect: Add EPSS L3 compatible for SA8775P
  interconnect: core: Add dynamic id allocation support
  interconnect: qcom: Add multidev EPSS L3 support
  interconnect: qcom: icc-rpmh: Add dynamic icc node id support
  interconnect: qcom: sa8775p: Add dynamic icc node id support

Link: https://lore.kernel.org/r/20250415095343.32125-1-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

DTS example in the bindings should be indented with 2- or 4-spaces and
aligned with opening '- |', so correct any differences like 3-spaces or
mixtures 2- and 4-spaces in one binding.  While re-indenting, drop
unused labels.

No functional changes here, but saves some comments during reviews of
new patches built on existing code.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: "Rob Herring (Arm)" <robh@kernel.org>
Link: https://lore.kernel.org/r/20250324125302.82167-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Add Epoch Subsystem (EPSS) L3 interconnect provider binding on
SA8775P SoCs.
The L3 instance on the SA8775P SoC is similar to those on SoCs
like SM8250 and SC7280. These SoCs use the PERF register instead
of L3_REG for programming the performance level, which is managed
in the data associated with the target-specific compatibles.
Since the hardware remains the same across all EPSS-supporting SoCs,
the generic compatible is retained for all SoCs.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Link: https://lore.kernel.org/r/20250415095343.32125-2-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Add interconnect support for SM8750 SoC.

The Qualcomm Technologies, Inc. SM8750 SoC is the latest in the line of
consumer mobile device SoCs.

* icc-sm8750
  dt-bindings: interconnect: add interconnect bindings for SM8750
  interconnect: qcom: Add interconnect provider driver for SM8750
  interconnect: sm8750: Add missing const to static qcom_icc_desc

Link: https://lore.kernel.org/r/20241204-sm8750_master_interconnects-v3-0-3d9aad4200e9@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Document the SM8750 BWMONs, which has one instance per cluster of
BWMONv4.

Signed-off-by: Shivnandan Kumar <quic_kshivnan@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Link: https://lore.kernel.org/r/20250113-sm8750_bwmon_master-v1-1-f082da3a3308@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Document the OSM L3 found in the Qualcomm SM8650 platform.

Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20250110-topic-sm8650-ddr-bw-scaling-v1-1-041d836b084c@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Document QCS615 BWMONs, which includes one BWMONv4 instance for CPU to
LLCC path bandwidth monitoring and one BWMONv5 instance for LLCC to DDR
path bandwidth monitoring.

Signed-off-by: Lijuan Gao <quic_lijuang@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241218-add_bwmon_support_for_qcs615-v1-1-680d798a19e5@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Add interconnect device bindings. These devices can be used
to describe any RPMh and NoC based interconnect devices.

Signed-off-by: Raviteja Laggyshetty <quic_rlaggysh@quicinc.com>
Signed-off-by: Melody Olvera <quic_molvera@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241204-sm8750_master_interconnects-v3-1-3d9aad4200e9@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Add driver for the network of connects present on the SAR2130P platform.

* icc-sar2130p
  dt-bindings: interconnect: qcom: document SAR2130P NoC
  interconnect: qcom: add support for SAR2130P

Link: https://lore.kernel.org/r/20241018-sar2130p-icc-v2-0-c58c73dcd19d@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>

Add interconnect dt-bindings and driver support for Qualcomm QCS615 SoC.

* icc-qcs615
  dt-bindings: interconnect: document the RPMh Network-On-Chip interconnect in QCS615 SoC
  interconnect: qcom: add QCS615 interconnect provider driver

Link: https://lore.kernel.org/r/20240924143958.25-1-quic_rlaggysh@quicinc.com
Signed-off-by: Georgi Djakov <djakov@kernel.org>