linux.git/Documentation/devicetree/bindings/i3c, branch master Linux kernel source tree dt-bindings: i3c: Add mipi-i3c-static-method to support SETAASA 2026-07-31T07:28:14+00:00 Akhil R akhilrajeev@nvidia.com 2026-07-28T06:59:43+00:00 81e7c27b0d5cb3029fc01374c3a96019d3a9e673 Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C Discovery and Configuration Specification [1] to specify which discovery method an I3C device supports during bus initialization. The property is a bitmap, where a bit value of 1 indicates support for that method, and 0 indicates lack of support. Bit 0: SETDASA CCC (Direct) Bit 1: SETAASA CCC (Broadcast) Bit 2: Other CCC (vendor / standards extension) All other bits are reserved. It is specifically needed when an I3C device requires SETAASA for the address assignment. SETDASA will be supported by default if this property is absent, which means for now the property just serves as a flag to enable SETAASA, but keep the property as a bitmap to align with the specifications. [1] https://www.mipi.org/mipi-disco-for-i3c-download Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Akhil R <akhilrajeev@nvidia.com> Link: https://patch.msgid.link/20260728065955.809445-2-akhilrajeev@nvidia.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add the 'mipi-i3c-static-method' property mentioned in the MIPI I3C
Discovery and Configuration Specification [1] to specify which discovery
method an I3C device supports during bus initialization. The property is
a bitmap, where a bit value of 1 indicates support for that method, and 0
indicates lack of support.

Bit 0: SETDASA CCC (Direct)
Bit 1: SETAASA CCC (Broadcast)
Bit 2: Other CCC (vendor / standards extension)
All other bits are reserved.

It is specifically needed when an I3C device requires SETAASA for the
address assignment. SETDASA will be supported by default if this property
is absent, which means for now the property just serves as a flag to
enable SETAASA, but keep the property as a bitmap to align with the
specifications.

[1] https://www.mipi.org/mipi-disco-for-i3c-download

Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Akhil R <akhilrajeev@nvidia.com>
Link: https://patch.msgid.link/20260728065955.809445-2-akhilrajeev@nvidia.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: dw: Document missing optional core reset 2026-07-31T07:28:14+00:00 Shubham Patil shubhamsanjay.patil@amd.com 2026-07-20T07:35:09+00:00 dce830367d5f8b56520993a5f121cfd35773cabc The DesignWare I3C master IP supports a core reset input, but the binding is missing the corresponding reset description. Document the optional reset property. Keep it optional because the reset line is integration-specific. Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260720073510.1869623-2-shubhamsanjay.patil@amd.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
The DesignWare I3C master IP supports a core reset input, but the
binding is missing the corresponding reset description.

Document the optional reset property. Keep it optional because the
reset line is integration-specific.

Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://patch.msgid.link/20260720073510.1869623-2-shubhamsanjay.patil@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: cdns: add Axiado AX3005 I3C variant 2026-07-31T07:28:14+00:00 Swark Yang syang@axiado.com 2026-07-17T03:51:11+00:00 bc0bc485c873743fb212f0d92d45686d5da8077a Add binding for Axiado AX3005 I3C master. So far, no changes are known, so it can fall back to the cdns,i3c-master compatible. Signed-off-by: Swark Yang <syang@axiado.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Link: https://patch.msgid.link/20260716-upstream-axiado-ax3005-upstream-v3-4-c429095143ec@axiado.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add binding for Axiado AX3005 I3C master. So far, no changes
are known, so it can fall back to the cdns,i3c-master compatible.

Signed-off-by: Swark Yang <syang@axiado.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://patch.msgid.link/20260716-upstream-axiado-ax3005-upstream-v3-4-c429095143ec@axiado.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: Add AMD I3C master controller support 2026-07-31T07:28:12+00:00 Manikanta Guntupalli manikanta.guntupalli@amd.com 2026-07-09T06:42:32+00:00 9ddb4d35817706c379d8d82c892895958c1571c4 Add device tree binding documentation for the AMD I3C master controller version 1.0. Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com> Co-developed-by: Shubham Patil <shubhamsanjay.patil@amd.com> Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com> Link: https://patch.msgid.link/20260709064233.1451482-2-shubhamsanjay.patil@amd.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add device tree binding documentation for the AMD I3C master controller
version 1.0.

Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli@amd.com>
Co-developed-by: Shubham Patil <shubhamsanjay.patil@amd.com>
Signed-off-by: Shubham Patil <shubhamsanjay.patil@amd.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
Link: https://patch.msgid.link/20260709064233.1451482-2-shubhamsanjay.patil@amd.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: mipi-i3c-hci: add Microchip SAMA7D65 compatible 2026-06-14T20:38:43+00:00 Manikandan Muralidharan manikandan.m@microchip.com 2026-05-25T09:24:01+00:00 9092105b87afcb38913919af82b38370ba69a7ea Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C HCI binding. The Microchip SAMA7D65 I3C controller is based on the MIPI HCI specification but requires two clocks, so add a conditional constraint when this compatible is present. Acked-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com> Link: https://patch.msgid.link/20260525092405.1514213-2-manikandan.m@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add the microchip,sama7d65-i3c-hci compatible string to the MIPI I3C
HCI binding. The Microchip SAMA7D65 I3C controller is based on the
MIPI HCI specification but requires two clocks, so add a conditional
constraint when this compatible is present.

Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Signed-off-by: Manikandan Muralidharan <manikandan.m@microchip.com>
Link: https://patch.msgid.link/20260525092405.1514213-2-manikandan.m@microchip.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: snps: Add Altera SoCFPGA compatible 2025-11-08T21:50:46+00:00 Adrian Ng Ho Yin adrianhoyin.ng@altera.com 2025-11-04T07:29:06+00:00 8d1d2c408cc05021970df5dd7d41133d220cf851 Add the "altr,agilex5-dw-i3c-master" compatible string to the Synopsys DesignWare I3C master binding. This allow Agilex5 to use the generic DW I3C master controller while applying any required platform-specific quirks. Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://patch.msgid.link/4ef059b129e9457eaadcfa6b996b9b6b000c7dba.1762237922.git.adrianhoyin.ng@altera.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add the "altr,agilex5-dw-i3c-master" compatible string to the
Synopsys DesignWare I3C master binding. This allow Agilex5 to
use the generic DW I3C master controller while applying any
required platform-specific quirks.

Signed-off-by: Adrian Ng Ho Yin <adrianhoyin.ng@altera.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://patch.msgid.link/4ef059b129e9457eaadcfa6b996b9b6b000c7dba.1762237922.git.adrianhoyin.ng@altera.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: renesas,i3c: Add RZ/V2H(P) and RZ/V2N support 2025-09-16T15:06:43+00:00 Lad Prabhakar prabhakar.mahadev-lad.rj@bp.renesas.com 2025-09-08T09:39:30+00:00 c5d0df4945085098e4778b27267a225efacf4d2a Add device tree binding support for the I3C Bus Interface on Renesas RZ/V2H(P) and RZ/V2N SoCs. The I3C IP on these SoCs is identical to that found on the RZ/G3E SoC. Add new compatible strings "renesas,r9a09g056-i3c" for RZ/V2N and "renesas,r9a09g057-i3c" for RZ/V2H(P). Both variants use "renesas,r9a09g047-i3c" as a fallback compatible to indicate hardware compatibility with the RZ/G3E implementation. Update the title to be more generic as it now covers multiple SoC families beyond just RZ/G3S and RZ/G3E. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Link: https://lore.kernel.org/r/20250908093930.12591-1-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add device tree binding support for the I3C Bus Interface on Renesas
RZ/V2H(P) and RZ/V2N SoCs. The I3C IP on these SoCs is identical to
that found on the RZ/G3E SoC.

Add new compatible strings "renesas,r9a09g056-i3c" for RZ/V2N and
"renesas,r9a09g057-i3c" for RZ/V2H(P). Both variants use
"renesas,r9a09g047-i3c" as a fallback compatible to indicate hardware
compatibility with the RZ/G3E implementation.

Update the title to be more generic as it now covers multiple SoC
families beyond just RZ/G3S and RZ/G3E.

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20250908093930.12591-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
dt-bindings: i3c: Add adi-i3c-master 2025-09-16T15:06:43+00:00 Jorge Marques jorge.marques@analog.com 2025-08-27T13:51:58+00:00 f3317e8c36a26d3374f29b8475982a96c6d44ccf Add bindings doc for ADI I3C Controller IP core, a FPGA synthesizable IP core that implements the MIPI I3C Basic controller specification. The IP Core is versioned following Semantic Versioning 2.0.0 and ADI's open-source HDL guidelines for devicetree bindings and drivers. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jorge Marques <jorge.marques@analog.com> Link: https://lore.kernel.org/r/20250827-adi-i3c-master-v9-1-04413925abe1@analog.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add bindings doc for ADI I3C Controller IP core, a FPGA synthesizable IP
core that implements the MIPI I3C Basic controller specification.
The IP Core is versioned following Semantic Versioning 2.0.0 and
ADI's open-source HDL guidelines for devicetree bindings and drivers.

Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Jorge Marques <jorge.marques@analog.com>
Link: https://lore.kernel.org/r/20250827-adi-i3c-master-v9-1-04413925abe1@analog.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Merge tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux 2025-08-03T21:12:02+00:00 Linus Torvalds torvalds@linux-foundation.org 2025-08-03T21:12:02+00:00 546b0ad6a87297a4268bc336aea57173008428e8 Pull i3c updates from Alexandre Belloni: "New driver: - Renesas I3C controller Subsystem: - use adapter timeout value for I2C transfers - don't fail if GETHDRCAP is unsupported - replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP Drivers: - svc: Fix npcm845 FIFO_EMPTY quirk" * tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux: (25 commits) i3c: add missing include to internal header i3c: dw: Remove redundant pm_runtime_mark_last_busy() calls i3c: master: svc: Remove redundant pm_runtime_mark_last_busy() calls i3c: master: svc: Fix npcm845 FIFO_EMPTY quirk i3c: master: Add basic driver for the Renesas I3C controller dt-bindings: i3c: Add Renesas I3C controller i3c: Add more parameters for controllers to the header i3c: Standardize defines for specification parameters i3c: fix module_i3c_i2c_driver() with I3C=n i3c: master: cdns: Simplify handling clocks in probe() i3c: Fix i3c_device_do_priv_xfers() kernel-doc indentation i3c: master: dw: Use i3c_writel_fifo() and i3c_readl_fifo() i3c: master: cdns: Use i3c_writel_fifo() and i3c_readl_fifo() i3c: master: Add inline i3c_readl_fifo() and i3c_writel_fifo() i3c: prefix hexadecimal entries in sysfs i3c: master: cdns: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP i3c: dw: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP i3c: master: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP i3c: don't fail if GETHDRCAP is unsupported i3c: add patchwork entry to MAINTAINERS ... 
Pull i3c updates from Alexandre Belloni:
 "New driver:
   - Renesas I3C controller

  Subsystem:
   - use adapter timeout value for I2C transfers
   - don't fail if GETHDRCAP is unsupported
   - replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP

  Drivers:
   - svc: Fix npcm845 FIFO_EMPTY quirk"

* tag 'i3c/for-6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/i3c/linux: (25 commits)
  i3c: add missing include to internal header
  i3c: dw: Remove redundant pm_runtime_mark_last_busy() calls
  i3c: master: svc: Remove redundant pm_runtime_mark_last_busy() calls
  i3c: master: svc: Fix npcm845 FIFO_EMPTY quirk
  i3c: master: Add basic driver for the Renesas I3C controller
  dt-bindings: i3c: Add Renesas I3C controller
  i3c: Add more parameters for controllers to the header
  i3c: Standardize defines for specification parameters
  i3c: fix module_i3c_i2c_driver() with I3C=n
  i3c: master: cdns: Simplify handling clocks in probe()
  i3c: Fix i3c_device_do_priv_xfers() kernel-doc indentation
  i3c: master: dw: Use i3c_writel_fifo() and i3c_readl_fifo()
  i3c: master: cdns: Use i3c_writel_fifo() and i3c_readl_fifo()
  i3c: master: Add inline i3c_readl_fifo() and i3c_writel_fifo()
  i3c: prefix hexadecimal entries in sysfs
  i3c: master: cdns: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP
  i3c: dw: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP
  i3c: master: replace ENOTSUPP with SUSV4-compliant EOPNOTSUPP
  i3c: don't fail if GETHDRCAP is unsupported
  i3c: add patchwork entry to MAINTAINERS
  ...
dt-bindings: i3c: Add Renesas I3C controller 2025-07-30T23:33:20+00:00 Tommaso Merciai tommaso.merciai.xr@bp.renesas.com 2025-07-24T09:41:42+00:00 94e611b5b9ef3a1d9ba77f41343e95155a5091d2 Add Renesas I3C controller which is available in R9A08G045 (RZ/G3S) and R9A09G047 (RZ/G3E) SoCs. Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Link: https://lore.kernel.org/r/20250724094146.6443-4-wsa+renesas@sang-engineering.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com> 
Add Renesas I3C controller which is available in R9A08G045 (RZ/G3S) and
R9A09G047 (RZ/G3E) SoCs.

Signed-off-by: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20250724094146.6443-4-wsa+renesas@sang-engineering.com
Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>