<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux.git/Documentation/devicetree/bindings/firmware, branch for-next</title>
<subtitle>Linux kernel source tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/'/>
<entry>
<title>Merge tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux into soc/drivers</title>
<updated>2024-11-13T17:38:56+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-11-13T17:38:51+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=1876c788bba174660b538dcf5d1bc2b75d7f6d66'/>
<id>1876c788bba174660b538dcf5d1bc2b75d7f6d66</id>
<content type='text'>
A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A few more Qualcomm driver updates for v6.13

Make the Adreno driver invoke the SMMU aperture setup firmware function,
which is required to allow the GPU to manage per-process page tables in
some firmware versions - as an example Rb3Gen2 has no GPU without this.

Add X1E Devkit to the list of devices that has functional EFI variable
access through the uefisecapp.

Flip the "manual slice configuration quirk" in the Qualcomm LLCC driver,
as this only applies to a single platform, and introduce support for
QCS8300, QCS615, SAR2130P, and SAR1130P.

Lastly, add IPQ5424 and IPQ5404 to the Qualcomm socinfo driver.

* tag 'qcom-drivers-for-6.13-2' of https://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux:
  soc: qcom: ice: Remove the device_link field in qcom_ice
  drm/msm/adreno: Setup SMMU aparture for per-process page table
  firmware: qcom: scm: Introduce CP_SMMU_APERTURE_ID
  soc: qcom: socinfo: add IPQ5424/IPQ5404 SoC ID
  dt-bindings: arm: qcom,ids: add SoC ID for IPQ5424/IPQ5404
  soc: qcom: llcc: Flip the manual slice configuration condition
  dt-bindings: firmware: qcom,scm: Document sm8750 SCM
  firmware: qcom: uefisecapp: Allow X1E Devkit devices
  soc: qcom: llcc: Add LLCC configuration for the QCS8300 platform
  dt-bindings: cache: qcom,llcc: Document the QCS8300 LLCC
  soc: qcom: llcc: Add configuration data for QCS615
  dt-bindings: cache: qcom,llcc: Document the QCS615 LLCC
  soc: qcom: llcc: add support for SAR2130P and SAR1130P
  soc: qcom: llcc: use deciman integers for bit shift values
  dt-bindings: cache: qcom,llcc: document SAR2130P and SAR1130P

Link: https://lore.kernel.org/r/20241113032425.356306-1-andersson@kernel.org
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into soc/drivers</title>
<updated>2024-11-12T14:56:51+00:00</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2024-11-12T14:56:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=ec72578ef9453f9352719b5d5d3b7c777ccb09c4'/>
<id>ec72578ef9453f9352719b5d5d3b7c777ccb09c4</id>
<content type='text'>
Arm SCMI updates for v6.13

Just couple of main additions:
1. Support for variable I/O width within ARM SCMI shared memory area.

   Some shared memory areas might only support a certain access width,
   such as 32-bit, which memcpy_{from,to}_io() does not adhere to at least
   on ARM64 by making both 8-bit and 64-bit accesses to such memory.

    This support updates the shmem layer to support reading from and
    writing to such shared memory area using the specified I/O width
    in the Device Tree. The various transport layers making use of the
    shmem.c code are updated accordingly to pass the I/O accessors that
    they store. The device tree bindings are also updated for the same.

2. Extension of SCMI transport bindings to add more properties

   SCMI transports are characterized by a number of properties. The
   values assumed by some of them tightly depend on the choices taken at
   design time and on the overall archiecture of the specific platform:
   things like timeouts, maximum message size and number of in-flight
   messages are closely tied to the architecture of the platform like
   number of SCMI agents on the system, physical memory available to the
   SCMI platform and so on. Such details are not discoverable as they are
   outside the scope of the SCMI protocol specification.

   Currently such properties are simple default values defined at build
   time, but the increasing number and variety of platforms using SCMI
   with a wide range of designs has increased the need to have a way to
   describe such properties across all these platforms.

Apart from the above two, there is one NULL pointer dereference fix for
very age old SCPI protocol driver which seems to be still in use on few
platforms.

* tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  firmware: arm_scpi: Check the DVFS OPP count returned by the firmware
  firmware: arm_scmi: Relocate atomic_threshold to scmi_desc
  firmware: arm_scmi: Use max_msg and max_msg_size devicetree properties
  dt-bindings: firmware: arm,scmi: Introduce more transport properties
  firmware: arm_scmi: Calculate virtio PDU max size dynamically
  firmware: arm_scmi: Account for SHMEM memory overhead
  firmware: arm_scmi: Support 'reg-io-width' property for shared memory
  dt-bindings: sram: Document reg-io-width property
  firmware: arm_scmi: Use vendor string in max-rx-timeout-ms
  dt-bindings: firmware: arm,scmi: Add missing vendor string
  firmware: arm_scmi: Reject clear channel request on A2P
  firmware: arm_scmi: Fix slab-use-after-free in scmi_bus_notifier()

Link: https://lore.kernel.org/r/20241106110727.4007489-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Arm SCMI updates for v6.13

Just couple of main additions:
1. Support for variable I/O width within ARM SCMI shared memory area.

   Some shared memory areas might only support a certain access width,
   such as 32-bit, which memcpy_{from,to}_io() does not adhere to at least
   on ARM64 by making both 8-bit and 64-bit accesses to such memory.

    This support updates the shmem layer to support reading from and
    writing to such shared memory area using the specified I/O width
    in the Device Tree. The various transport layers making use of the
    shmem.c code are updated accordingly to pass the I/O accessors that
    they store. The device tree bindings are also updated for the same.

2. Extension of SCMI transport bindings to add more properties

   SCMI transports are characterized by a number of properties. The
   values assumed by some of them tightly depend on the choices taken at
   design time and on the overall archiecture of the specific platform:
   things like timeouts, maximum message size and number of in-flight
   messages are closely tied to the architecture of the platform like
   number of SCMI agents on the system, physical memory available to the
   SCMI platform and so on. Such details are not discoverable as they are
   outside the scope of the SCMI protocol specification.

   Currently such properties are simple default values defined at build
   time, but the increasing number and variety of platforms using SCMI
   with a wide range of designs has increased the need to have a way to
   describe such properties across all these platforms.

Apart from the above two, there is one NULL pointer dereference fix for
very age old SCPI protocol driver which seems to be still in use on few
platforms.

* tag 'scmi-updates-6.13' of https://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  firmware: arm_scpi: Check the DVFS OPP count returned by the firmware
  firmware: arm_scmi: Relocate atomic_threshold to scmi_desc
  firmware: arm_scmi: Use max_msg and max_msg_size devicetree properties
  dt-bindings: firmware: arm,scmi: Introduce more transport properties
  firmware: arm_scmi: Calculate virtio PDU max size dynamically
  firmware: arm_scmi: Account for SHMEM memory overhead
  firmware: arm_scmi: Support 'reg-io-width' property for shared memory
  dt-bindings: sram: Document reg-io-width property
  firmware: arm_scmi: Use vendor string in max-rx-timeout-ms
  dt-bindings: firmware: arm,scmi: Add missing vendor string
  firmware: arm_scmi: Reject clear channel request on A2P
  firmware: arm_scmi: Fix slab-use-after-free in scmi_bus_notifier()

Link: https://lore.kernel.org/r/20241106110727.4007489-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: qcom,scm: Document sm8750 SCM</title>
<updated>2024-11-05T22:44:25+00:00</updated>
<author>
<name>Melody Olvera</name>
<email>quic_molvera@quicinc.com</email>
</author>
<published>2024-10-21T23:04:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=4cadd106208143a919c957171a0634e16fd32f82'/>
<id>4cadd106208143a919c957171a0634e16fd32f82</id>
<content type='text'>
Document the scm compatible for sm8750 SoC.

Signed-off-by: Melody Olvera &lt;quic_molvera@quicinc.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20241021230427.2632466-1-quic_molvera@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Document the scm compatible for sm8750 SoC.

Signed-off-by: Melody Olvera &lt;quic_molvera@quicinc.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20241021230427.2632466-1-quic_molvera@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: qcom,scm: document SCM on QCS8300 SoCs</title>
<updated>2024-10-29T20:07:02+00:00</updated>
<author>
<name>Zhenhua Huang</name>
<email>quic_zhenhuah@quicinc.com</email>
</author>
<published>2024-09-11T08:03:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=fc0dead9b7ae33ad9266d4a8e43232f673ae8710'/>
<id>fc0dead9b7ae33ad9266d4a8e43232f673ae8710</id>
<content type='text'>
Document scm compatible for the Qualcomm QCS8300 SoC. It is an interface
to communicate to the secure firmware.

Signed-off-by: Zhenhua Huang &lt;quic_zhenhuah@quicinc.com&gt;
Signed-off-by: Jingyi Wang &lt;quic_jingyw@quicinc.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-2-de8641b3eaa1@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Document scm compatible for the Qualcomm QCS8300 SoC. It is an interface
to communicate to the secure firmware.

Signed-off-by: Zhenhua Huang &lt;quic_zhenhuah@quicinc.com&gt;
Signed-off-by: Jingyi Wang &lt;quic_jingyw@quicinc.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
Link: https://lore.kernel.org/r/20240911-qcs8300_binding-v2-2-de8641b3eaa1@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: qcom,scm: document support for SA8255p</title>
<updated>2024-10-29T20:03:39+00:00</updated>
<author>
<name>Nikunj Kela</name>
<email>quic_nkela@quicinc.com</email>
</author>
<published>2024-09-05T18:30:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=b4bd100500c0be2a9ac1655977f54806d1eb8195'/>
<id>b4bd100500c0be2a9ac1655977f54806d1eb8195</id>
<content type='text'>
Add a compatible for the SA8255p platform's Secure Channel Manager
firmware interface.

Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Nikunj Kela &lt;quic_nkela@quicinc.com&gt;
Link: https://lore.kernel.org/r/20240905183016.3742735-1-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add a compatible for the SA8255p platform's Secure Channel Manager
firmware interface.

Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Signed-off-by: Nikunj Kela &lt;quic_nkela@quicinc.com&gt;
Link: https://lore.kernel.org/r/20240905183016.3742735-1-quic_nkela@quicinc.com
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: arm,scmi: Introduce more transport properties</title>
<updated>2024-10-28T14:51:10+00:00</updated>
<author>
<name>Cristian Marussi</name>
<email>cristian.marussi@arm.com</email>
</author>
<published>2024-10-28T12:01:47+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=5654d37268bcbae4727d693e35d8e55e13d96fee'/>
<id>5654d37268bcbae4727d693e35d8e55e13d96fee</id>
<content type='text'>
Depending on specific hardware and firmware design choices, it may be
possible for different platforms to end up having different requirements
regarding the same transport characteristics.

Introduce max-msg-size and max-msg properties to describe such platform
specific transport constraints, since they cannot be discovered otherwise.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Message-Id: &lt;20241028120151.1301177-4-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Depending on specific hardware and firmware design choices, it may be
possible for different platforms to end up having different requirements
regarding the same transport characteristics.

Introduce max-msg-size and max-msg properties to describe such platform
specific transport constraints, since they cannot be discovered otherwise.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Message-Id: &lt;20241028120151.1301177-4-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: arm,scmi: Add missing vendor string</title>
<updated>2024-10-28T14:48:48+00:00</updated>
<author>
<name>Cristian Marussi</name>
<email>cristian.marussi@arm.com</email>
</author>
<published>2024-10-28T12:01:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7bf46ec090b9e6c9ab08d8006b4eefba2cd5a7f5'/>
<id>7bf46ec090b9e6c9ab08d8006b4eefba2cd5a7f5</id>
<content type='text'>
Recently introduced max-rx-timeout-ms optionao property is missing a
vendor prefix.

Add the vendor prefix so that it aligns with the new properties that
are about to get added soon.

Fixes: 3a5e6ab06eab ("dt-bindings: firmware: arm,scmi: Introduce property max-rx-timeout-ms")
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Message-Id: &lt;20241028120151.1301177-7-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Recently introduced max-rx-timeout-ms optionao property is missing a
vendor prefix.

Add the vendor prefix so that it aligns with the new properties that
are about to get added soon.

Fixes: 3a5e6ab06eab ("dt-bindings: firmware: arm,scmi: Introduce property max-rx-timeout-ms")
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Message-Id: &lt;20241028120151.1301177-7-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: qcom,scm: Add SAR2130P compatible</title>
<updated>2024-10-23T04:10:58+00:00</updated>
<author>
<name>Dmitry Baryshkov</name>
<email>dmitry.baryshkov@linaro.org</email>
</author>
<published>2024-10-17T18:20:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=e19bc8b2249b13a34bb2db82755cee5a1dad0ef2'/>
<id>e19bc8b2249b13a34bb2db82755cee5a1dad0ef2</id>
<content type='text'>
Document compatible for the SCM firmware interface on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20241017-sar2130p-scm-v1-1-cc74a6b75c94@linaro.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Document compatible for the SCM firmware interface on SAR2130P platform.

Signed-off-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20241017-sar2130p-scm-v1-1-cc74a6b75c94@linaro.org
Signed-off-by: Bjorn Andersson &lt;andersson@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: Add i.MX95 SCMI Extension protocol</title>
<updated>2024-08-28T20:53:40+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-08-23T09:05:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=7d2b23fda9961e7bfdd063a1708445b101a831c5'/>
<id>7d2b23fda9961e7bfdd063a1708445b101a831c5</id>
<content type='text'>
Add i.MX SCMI Extension protocols bindings for:
- Battery Backed Module(BBM) Protocol
  This contains persistent storage (GPR), an RTC, and the ON/OFF button.
  The protocol can also provide access to similar functions implemented via
  external board components.
- MISC Protocol.
  This includes controls that are misc settings/actions that must be
  exposed from the SM to agents. They are device specific and are usually
  define to access bit fields in various mix block control modules,
  IOMUX_GPR, and other GPR/CSR owned by the SM.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Reviewed-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Message-Id: &lt;20240823-imx95-bbm-misc-v2-v8-1-e600ed9e9271@nxp.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add i.MX SCMI Extension protocols bindings for:
- Battery Backed Module(BBM) Protocol
  This contains persistent storage (GPR), an RTC, and the ON/OFF button.
  The protocol can also provide access to similar functions implemented via
  external board components.
- MISC Protocol.
  This includes controls that are misc settings/actions that must be
  exposed from the SM to agents. They are device specific and are usually
  define to access bit fields in various mix block control modules,
  IOMUX_GPR, and other GPR/CSR owned by the SM.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Reviewed-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
Message-Id: &lt;20240823-imx95-bbm-misc-v2-v8-1-e600ed9e9271@nxp.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>dt-bindings: firmware: arm,scmi: Introduce property max-rx-timeout-ms</title>
<updated>2024-08-18T19:22:16+00:00</updated>
<author>
<name>Peng Fan</name>
<email>peng.fan@nxp.com</email>
</author>
<published>2024-07-30T14:47:03+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux.git/commit/?id=3a5e6ab06eabcf105a83199be09453ff1475e77e'/>
<id>3a5e6ab06eabcf105a83199be09453ff1475e77e</id>
<content type='text'>
System Controller Management Interface(SCMI) firmwares might have different
designs depending on the platform: the maximum receive channel timeout
value might vary depending on the specific underlying hardware and firmware
design choices.

Introduce the general property max-rx-timeout-ms property to describe the
transport needs of a specific platform design.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
[Cristian: reworded commit message, s/mailbox/transport in description]
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Tested-by: Peng Fan &lt;peng.fan@nxp.com&gt;  #i.MX95 19x19 EVK
Message-Id: &lt;20240730144707.1647025-3-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
System Controller Management Interface(SCMI) firmwares might have different
designs depending on the platform: the maximum receive channel timeout
value might vary depending on the specific underlying hardware and firmware
design choices.

Introduce the general property max-rx-timeout-ms property to describe the
transport needs of a specific platform design.

Reviewed-by: Rob Herring (Arm) &lt;robh@kernel.org&gt;
Signed-off-by: Peng Fan &lt;peng.fan@nxp.com&gt;
[Cristian: reworded commit message, s/mailbox/transport in description]
Signed-off-by: Cristian Marussi &lt;cristian.marussi@arm.com&gt;
Tested-by: Peng Fan &lt;peng.fan@nxp.com&gt;  #i.MX95 19x19 EVK
Message-Id: &lt;20240730144707.1647025-3-cristian.marussi@arm.com&gt;
Signed-off-by: Sudeep Holla &lt;sudeep.holla@arm.com&gt;
</pre>
</div>
</content>
</entry>
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