linux.git/Documentation/devicetree/bindings/clock, branch master Linux kernel source tree Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 2026-08-26T18:14:30+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-26T18:14:30+00:00 502d45774af09f1c681c754c4b7cdfb5d7f72fd9 Pull clk updates from Stephen Boyd: "Mostly the usual clk driver updates and new SoC additions plus non-critical data fixes for things that weren't used yet. One thing that's new here in the core is SSC spread spectrum support (SSC) in the clk provider API. The idea is that DT authors will configure SSC for certain clks and they'll be configured at clk provider registration time or when a consumer device is probed, similar to how we handle assigned clk rates or parents. On the clk driver side we have Qualcomm adding almost half the diff because they add support for 4 different SoCs and then a long tail of other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more SoC support this time around. Luckily it's mostly clk data for these new SoCs because the actual clk_ops are already there. Beyond the new drivers we get all the little fixups for more compilation coverage or usage of more modern APIs. That all looks normal. Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to help out with maintaining the clk subsystem. The current working model is already semi-distributed in that silicon vendors typically take care of their drivers and send me pull requests but I'm becoming a bottleneck for new drivers and core framework review because this has become a 100% volunteer effort on my part. Mike is stepping down after all these years (thanks Mike!) and that jump started the conversation around finding co-maintainers. Brian and Jerome have graciously offered to help me with the work load, meaning in the future they'll be sending pull requests and committing directly to the clk.git tree. They've both been around on the list for a while, I've met them both in person, and they've been making changes to the core clk framework along with helping review patches so I'm pretty confident this will work well. Core: - devm_clk_bulk_get_enable() consumer API - devm_clk_hw_register_composite_pdata() provider API - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs - Divider clk rounding improved (and tested) New Drivers: - Cix Sky1 audio subsystem (AUDSS) - UltraRISC DP1000 - MediaTek MT8173 MFG_TOP - Si549 - Aspeed AST2700 PECI - Airoha EN7523 PCIe - Rockchip RV1106 - Mobileye EyeQ7H - Qualcomm Maili GCC, TCSR, RPMh, and video clks - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks - Qualcomm Nord display and graphics clks - Qualcomm Glymur camera and EVA clks - Qualcomm Hawi video clks - Amlogic A9 AO and peripheral clks - Renesas R-Car X5H (R8A78000) CPG" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: samsung: Don't include <linux/mod_devicetable.h> clk: at91: Read "reg" with helper clk: renesas: Add R-Car X5H CPG driver clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator ... 
Pull clk updates from Stephen Boyd:
 "Mostly the usual clk driver updates and new SoC additions plus
  non-critical data fixes for things that weren't used yet.

  One thing that's new here in the core is SSC spread spectrum support
  (SSC) in the clk provider API. The idea is that DT authors will
  configure SSC for certain clks and they'll be configured at clk
  provider registration time or when a consumer device is probed,
  similar to how we handle assigned clk rates or parents.

  On the clk driver side we have Qualcomm adding almost half the diff
  because they add support for 4 different SoCs and then a long tail of
  other SoCs like Mediatek, Renesas, Rockchip, SpaceMiT, etc. add more
  SoC support this time around. Luckily it's mostly clk data for these
  new SoCs because the actual clk_ops are already there. Beyond the new
  drivers we get all the little fixups for more compilation coverage or
  usage of more modern APIs. That all looks normal.

  Finally, I kinda buried the lede, I'm bringing on Brian and Jerome to
  help out with maintaining the clk subsystem. The current working model
  is already semi-distributed in that silicon vendors typically take
  care of their drivers and send me pull requests but I'm becoming a
  bottleneck for new drivers and core framework review because this has
  become a 100% volunteer effort on my part.

  Mike is stepping down after all these years (thanks Mike!) and that
  jump started the conversation around finding co-maintainers. Brian and
  Jerome have graciously offered to help me with the work load, meaning
  in the future they'll be sending pull requests and committing directly
  to the clk.git tree. They've both been around on the list for a while,
  I've met them both in person, and they've been making changes to the
  core clk framework along with helping review patches so I'm pretty
  confident this will work well.

  Core:
   - devm_clk_bulk_get_enable() consumer API
   - devm_clk_hw_register_composite_pdata() provider API
   - Spread Spectrum Clock (SSC) support via DT bindings and provider APIs
   - Divider clk rounding improved (and tested)

  New Drivers:
   - Cix Sky1 audio subsystem (AUDSS)
   - UltraRISC DP1000
   - MediaTek MT8173 MFG_TOP
   - Si549
   - Aspeed AST2700 PECI
   - Airoha EN7523 PCIe
   - Rockchip RV1106
   - Mobileye EyeQ7H
   - Qualcomm Maili GCC, TCSR, RPMh, and video clks
   - Qualcomm Shikra GCC, RPM, GPU, display, and audio clks
   - Qualcomm Nord display and graphics clks
   - Qualcomm Glymur camera and EVA clks
   - Qualcomm Hawi video clks
   - Amlogic A9 AO and peripheral clks
   - Renesas R-Car X5H (R8A78000) CPG"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (269 commits)
  clk: microchip: mpfs: fix regmap_update_bits() mask/val order
  clk: visconti: Make sure clk_init_data is fully initialized
  clk: ti: Make sure clk_init_data is fully initialized
  MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
  Drop Michael Turquette's clk maintainer entry
  clk: ti: composite: resolve parent clocks by DT index, not by name
  clk: ti: mux: resolve parent clocks by DT index, not by name
  clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
  dt-bindings: clock: ti,keystone-gate: Convert to DT schema
  dt-bindings: clock: ti: Convert APLL clock to DT schema
  clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
  dt-bindings: clock: ti,clockdomain: Convert to DT schema
  dt-bindings: clock: Correct white-space style
  clk: samsung: Don't include <linux/mod_devicetable.h>
  clk: at91: Read "reg" with helper
  clk: renesas: Add R-Car X5H CPG driver
  clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
  clk: rockchip: Add clock controller for the RV1106
  dt-bindings: clock: rockchip: Add RV1106 CRU support
  dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
  ...
Merge branches 'clk-pile' and 'clk-microchip' into clk-next 2026-08-20T23:51:47+00:00 Stephen Boyd sboyd@kernel.org 2026-08-20T23:51:47+00:00 dd8eb789f18c4c600f28e61176a02bcf3b790117 * clk-pile: (111 commits) clk: microchip: mpfs: fix regmap_update_bits() mask/val order clk: visconti: Make sure clk_init_data is fully initialized clk: ti: Make sure clk_init_data is fully initialized MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem Drop Michael Turquette's clk maintainer entry clk: ti: composite: resolve parent clocks by DT index, not by name clk: ti: mux: resolve parent clocks by DT index, not by name clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate() dt-bindings: clock: ti,keystone-gate: Convert to DT schema dt-bindings: clock: ti: Convert APLL clock to DT schema clk: zynq: pll: Fix kernel-doc after determine_rate() conversion dt-bindings: clock: ti,clockdomain: Convert to DT schema dt-bindings: clock: Correct white-space style clk: tegra: set up proper EMC clock implementation for Tegra114 clk: clocking-wizard: remove 20kHz restriction clk: clocking-wizard: optimize clock search clk: clocking-wizard: fix clock difference detection clk: mediatek: mt8135: Fix inverted gate control for devapc_ck clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig clk: tegra: support 48MHz clock for pll_p_out1 ... * clk-microchip: clk: at91: Read "reg" with helper 
* clk-pile: (111 commits)
  clk: microchip: mpfs: fix regmap_update_bits() mask/val order
  clk: visconti: Make sure clk_init_data is fully initialized
  clk: ti: Make sure clk_init_data is fully initialized
  MAINTAINERS: Add Brian Masney and Jerome Brunet as co-maintainers for clk subsystem
  Drop Michael Turquette's clk maintainer entry
  clk: ti: composite: resolve parent clocks by DT index, not by name
  clk: ti: mux: resolve parent clocks by DT index, not by name
  clk: devres: fix cleanup in devm_clk_get_optional_enabled_with_rate()
  dt-bindings: clock: ti,keystone-gate: Convert to DT schema
  dt-bindings: clock: ti: Convert APLL clock to DT schema
  clk: zynq: pll: Fix kernel-doc after determine_rate() conversion
  dt-bindings: clock: ti,clockdomain: Convert to DT schema
  dt-bindings: clock: Correct white-space style
  clk: tegra: set up proper EMC clock implementation for Tegra114
  clk: clocking-wizard: remove 20kHz restriction
  clk: clocking-wizard: optimize clock search
  clk: clocking-wizard: fix clock difference detection
  clk: mediatek: mt8135: Fix inverted gate control for devapc_ck
  clk: clocking-wizard: Program PLL CP/RES and lock parameters on reconfig
  clk: tegra: support 48MHz clock for pll_p_out1
  ...

* clk-microchip:
  clk: at91: Read "reg" with helper
Merge branches 'clk-imx', 'clk-rockchip', 'clk-samsung', 'clk-qcom' and 'clk-allwinner' into clk-next 2026-08-20T23:51:33+00:00 Stephen Boyd sboyd@kernel.org 2026-08-20T23:51:33+00:00 5d650f824df6c0db181164c36a73c0ab2286a24d * clk-imx: clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95 clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE() clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE() clk: imx: Add audio PLL debugfs for K-divider control * clk-rockchip: clk: rockchip: rk3576: fix source muxes for SPI0..SPI4 clk: rockchip: Add clock controller for the RV1106 dt-bindings: clock: rockchip: Add RV1106 CRU support clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src * clk-samsung: clk: samsung: Don't include <linux/mod_devicetable.h> clk: samsung: pll: use kzalloc_flex clk: samsung: cpu: use kzalloc_flex clk: samsung: use kzalloc_flex clk: samsung: exynos990: Fix PERIS gate clock parents clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK * clk-qcom: (94 commits) clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra clk: qcom: Return expected ENOMEM error on dynamic allocation failure clk: qcom: apss-ipq-pll: Add IPQ5210 support dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible clk: qcom: Add support for videocc driver on Qualcomm Maili SoC dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gpucc-qcm2290: Drop pm_clk handling clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs clk: qcom: dispcc-qcm2290: Enable runtime PM support clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC ... * clk-allwinner: clk: sunxi-ng: sun6i-rtc: add a733 support clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate clk: sunxi-ng: div: add read-only operation support clk: sunxi-ng: mux: fix determine helper rate propagation clk: sunxi-ng: mux: remove unneeded export clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration clk: sunxi-ng: sun6i-rtc: clean up DT usage clk: sunxi-ng: fix ccu probe clock unregister on error dt-bindings: rtc: sun6i: add sun60i-a733 support dt-bindings: rtc: sun6i: no clock-output-names on h616/r329 
* clk-imx:
  clk: imx95-blk-ctl: Fix REFCLK rise-fall mismatch on i.MX95
  clk: imx95-blk-ctl: Add func_out_en clock for i.MX9x PCIe
  clk: imx: imx8qxp: add missing MODULE_DEVICE_TABLE()
  clk: imx: imx8qxp-lpcg: add missing MODULE_DEVICE_TABLE()
  clk: imx: Add audio PLL debugfs for K-divider control

* clk-rockchip:
  clk: rockchip: rk3576: fix source muxes for SPI0..SPI4
  clk: rockchip: Add clock controller for the RV1106
  dt-bindings: clock: rockchip: Add RV1106 CRU support
  clk: rockchip: Fractional PLL coefficient on RK3588/RK3576 is two's complement
  clk: rockchip: Fix the fractional part denominator on RK3588/RK3576 PLLs
  clk: rockchip: rk3588: Allow VP2 the same sourcing options as other VPs
  clk: rockchip: rk3588: Don't change PLL rates when setting dclk_vop2_src

* clk-samsung:
  clk: samsung: Don't include <linux/mod_devicetable.h>
  clk: samsung: pll: use kzalloc_flex
  clk: samsung: cpu: use kzalloc_flex
  clk: samsung: use kzalloc_flex
  clk: samsung: exynos990: Fix PERIS gate clock parents
  clk: samsung: exynos990: Add PERIS TMU_SUB_PCLK gate
  dt-bindings: clock: exynos990: Add CLK_GOUT_PERIS_TMU_SUB_PCLK

* clk-qcom: (94 commits)
  clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra
  clk: qcom: Return expected ENOMEM error on dynamic allocation failure
  clk: qcom: apss-ipq-pll: Add IPQ5210 support
  dt-bindings: clock: qcom,a53pll: Add IPQ5210 compatible
  clk: qcom: Add support for videocc driver on Qualcomm Maili SoC
  dt-bindings: clock: qcom: Add Qualcomm Maili video clock controller
  dt-bindings: clock: qcom: Add Qualcomm Shikra GPU clock controller
  dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller
  clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable
  clk: qcom: gpucc-qcm2290: Keep the critical clocks always-on from probe
  clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
  clk: qcom: gpucc-qcm2290: Drop pm_clk handling
  clk: qcom: qcm2290: Update DISPCC and GPUCC GDSC *wait_val values
  clk: qcom: qcm2290: Add RETAIN_FF_ENABLE flag for DISPCC and GPUCC GDSCs
  clk: qcom: qcm2290: Set POLL_CFG_GDSCR flag for DISPCC and GPUCC GDSCs
  clk: qcom: dispcc-qcm2290: Enable runtime PM support
  clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model
  clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe
  dt-bindings: clock: qcom,qcm2290-dispcc: Add missing power-domains property
  clk: qcom: Add Audio Core clock controller support on Qualcomm Shikra SoC
  ...

* clk-allwinner:
  clk: sunxi-ng: sun6i-rtc: add a733 support
  clk: sunxi-ng: sun6i-rtc: split main oscillator div and gate
  clk: sunxi-ng: div: add read-only operation support
  clk: sunxi-ng: mux: fix determine helper rate propagation
  clk: sunxi-ng: mux: remove unneeded export
  clk: sunxi-ng: sun6i-rtc: Add feature bit for IOSC calibration
  clk: sunxi-ng: sun6i-rtc: clean up DT usage
  clk: sunxi-ng: fix ccu probe clock unregister on error
  dt-bindings: rtc: sun6i: add sun60i-a733 support
  dt-bindings: rtc: sun6i: no clock-output-names on h616/r329
Merge branches 'clk-renesas', 'clk-thead', 'clk-mobileye', 'clk-amlogic' and 'clk-spacemit' into clk-next 2026-08-20T23:51:21+00:00 Stephen Boyd sboyd@kernel.org 2026-08-20T23:51:21+00:00 a1476addb4631cc7d393adc057a20129b264520f * clk-renesas: clk: renesas: Add R-Car X5H CPG driver dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator clk: r9a08g045: Add clocks and resets for CAN-FD dt-bindings: clock: renesas,versaclock7: Update maintainer clk: renesas: r9a09g047: Add LVDS clocks and resets clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations clk: renesas: r9a08g046: Add USB2.0 clock and reset entries clk: renesas: r9a09g077: Add RTC clocks clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC clk: renesas: r9a08g046: Add clock and reset entries for GE3D clk: renesas: r9a08g046: Add clock and reset entries for SDHI clk: renesas: r9a09g047: Add audio clock and reset support dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID * clk-thead: clk: thead: allow COMPILE_TEST builds * clk-mobileye: clk: eyeq: Add EyeQ7H compatibles clk: eyeq: Drop PLL, dividers, and fixed factors structs clk: eyeq: Convert clocks declaration to eqc_clock clk: eyeq: Introduce a generic clock type clk: eyeq: Prefix the PLL registers with the PLL type clk: fixed-factor: Export __clk_hw_register_fixed_factor() clk: fixed-factor: Rework initialization with parent clocks reset: eyeq: Add EyeQ7H compatibles dt-bindings: soc: mobileye: Add EyeQ7H OLB * clk-amlogic: clk: amlogic: Add A9 peripherals clock controller driver dt-bindings: clock: Add Amlogic A9 peripherals clock controller clk: amlogic: Add A9 AO clock controller driver dt-bindings: clock: Add Amlogic A9 AO clock controller clk: meson: align gxbb_32k_clk_sel number of parents with actual count * clk-spacemit: clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers clk: spacemit: k3: fix i2s clock topology dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs clk: spacemit: k3: Add UFS refclk clock dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk clk: spacemit: k3: fix parent clock of UFS aclk 
* clk-renesas:
  clk: renesas: Add R-Car X5H CPG driver
  dt-bindings: clock: Document Renesas R-Car X5H Clock Pulse Generator
  clk: r9a08g045: Add clocks and resets for CAN-FD
  dt-bindings: clock: renesas,versaclock7: Update maintainer
  clk: renesas: r9a09g047: Add LVDS clocks and resets
  clk: renesas: r9a09g077: Add LCDC and PLL3 clock support for RZ/T2H display pipeline
  clk: renesas: rzv2h-cpg: Extract PLL calculation helpers into shared library
  clk: renesas: rzv2h-cpg: Use per-SoC PLL reference frequency for calculations
  clk: renesas: r9a08g046: Add USB2.0 clock and reset entries
  clk: renesas: r9a09g077: Add RTC clocks
  clk: renesas: cpg-mssr: Implement dedicated MSTP delay logic for RZ/T2H LCDC and RTC
  clk: renesas: r9a08g046: Add clock and reset entries for GE3D
  clk: renesas: r9a08g046: Add clock and reset entries for SDHI
  clk: renesas: r9a09g047: Add audio clock and reset support
  dt-bindings: clock: renesas: Add audio clock inputs for RZ/V2H family
  dt-bindings: clock: renesas,r9a09g077/87: Add PCLKRTC clock ID
  dt-bindings: clock: renesas,r9a09g077/87: Add LCDC_CLKD clock ID

* clk-thead:
  clk: thead: allow COMPILE_TEST builds

* clk-mobileye:
  clk: eyeq: Add EyeQ7H compatibles
  clk: eyeq: Drop PLL, dividers, and fixed factors structs
  clk: eyeq: Convert clocks declaration to eqc_clock
  clk: eyeq: Introduce a generic clock type
  clk: eyeq: Prefix the PLL registers with the PLL type
  clk: fixed-factor: Export __clk_hw_register_fixed_factor()
  clk: fixed-factor: Rework initialization with parent clocks
  reset: eyeq: Add EyeQ7H compatibles
  dt-bindings: soc: mobileye: Add EyeQ7H OLB

* clk-amlogic:
  clk: amlogic: Add A9 peripherals clock controller driver
  dt-bindings: clock: Add Amlogic A9 peripherals clock controller
  clk: amlogic: Add A9 AO clock controller driver
  dt-bindings: clock: Add Amlogic A9 AO clock controller
  clk: meson: align gxbb_32k_clk_sel number of parents with actual count

* clk-spacemit:
  clk: spacemit: k3: fix missing /2 factor in i2s sysclk dividers
  clk: spacemit: k3: fix i2s clock topology
  dt-bindings: soc: spacemit: k3: add i2s_sysclk, i2s_bclk_factor and i2s1_sysclk_src IDs
  clk: spacemit: k3: Add UFS refclk clock
  dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
  clk: spacemit: k3: fix parent clock of UFS aclk
Merge tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux 2026-08-19T17:32:34+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-19T17:32:34+00:00 c6cf4441a3a05bb7273ed022f3e56c4fc591da08 Pull devicetree updates from Rob Herring: - Add a DT maintainer profile document - Various dt-check-style improvements - Add a devres managed reserved memory region init function - Print node name on any skipped reserved memory regions - Correctly handle optional argument in of_parse_phandle_with_args_map() - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI DA8XX MSTPRI bus, and Xen VM bindings to DT schema format - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller, MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and QCom Shikra SCM firmware - A couple of syntax fixes found using PoC Rust implementation of dtschema tools - Clean-ups for typos, brackets, incorrect "::" usages, and white-space style * tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits) dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible dtc: dt-check-style: Simplify setting depth of DtsLine dtc: dt-check-style: Add missing /dts-v1/ to few test cases dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema media: dt-bindings: ti,da850-vpif: Convert to dt-schema dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer dt-bindings: arm: omap: Convert L4 interconnect to DT schema dt-bindings: power: Convert TI SmartReflex to DT schema of: reserved_mem: Introduce devres-managed initialization function dt-bindings: interrupt-controller: Add StarFive JHB100 plic dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller dt-bindings: Correct white-space style dt-bindings: fix typos and brackets docs: dt: submitting-patches: Mention expectation about dt-check-style docs: dt: maintainer: Add Devicetree and OF maintainer profile document docs: dt: writing-schema: Extend expectations about example part of binding dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU of: base: Handle optional argument in of_parse_phandle_with_args_map() dt-bindings: update Sudeep Holla's email address ... 
Pull devicetree updates from Rob Herring:

 - Add a DT maintainer profile document

 - Various dt-check-style improvements

 - Add a devres managed reserved memory region init function

 - Print node name on any skipped reserved memory regions

 - Correctly handle optional argument in
   of_parse_phandle_with_args_map()

 - Convert ti,keystone-reset, ti,da850-vpif, TI L4 interconnect, TI
   SmartReflex, microchip,pic32mzda-dmt, microchip,pic32mzda-wdt, TI
   DA8XX MSTPRI bus, and Xen VM bindings to DT schema format

 - Add bindings for StarFive JHB100 plic, Allwinner A733 NMI controller,
   MediaTek MT8173 GPU, QCom Shikra, Eliza, and Maili cpu-bwmon, and
   QCom Shikra SCM firmware

 - A couple of syntax fixes found using PoC Rust implementation of
   dtschema tools

 - Clean-ups for typos, brackets, incorrect "::" usages, and
   white-space style

* tag 'devicetree-for-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (40 commits)
  dt-bindings: interconnect: qcom-bwmon: Add Maili cpu-bwmon compatible
  dtc: dt-check-style: Simplify setting depth of DtsLine
  dtc: dt-check-style: Add missing /dts-v1/ to few test cases
  dt-bindings: power: reset: ti,keystone-reset: Convert to DT schema
  media: dt-bindings: ti,da850-vpif: Convert to dt-schema
  dt-bindings: devfreq: samsung,exynos-ppmu: Use standard regex syntax
  dt-bindings: interrupt-controller: mediatek,mt6577-sysirq: Drop invalid JSON pointer
  dt-bindings: arm: omap: Convert L4 interconnect to DT schema
  dt-bindings: power: Convert TI SmartReflex to DT schema
  of: reserved_mem: Introduce devres-managed initialization function
  dt-bindings: interrupt-controller: Add StarFive JHB100 plic
  dt-bindings: irq: sun7i-nmi: Document the Allwinner A733 NMI controller
  dt-bindings: Correct white-space style
  dt-bindings: fix typos and brackets
  docs: dt: submitting-patches: Mention expectation about dt-check-style
  docs: dt: maintainer: Add Devicetree and OF maintainer profile document
  docs: dt: writing-schema: Extend expectations about example part of binding
  dt-bindings: gpu: powervr-rogue: Add MediaTek MT8173 GPU
  of: base: Handle optional argument in of_parse_phandle_with_args_map()
  dt-bindings: update Sudeep Holla's email address
  ...
Merge tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 2026-08-19T02:36:32+00:00 Linus Torvalds torvalds@linux-foundation.org 2026-08-19T02:36:32+00:00 cbe8aadf1551f3f4a853f24b3b96d9f0eea49c53 Pull SoC devicetree updates from Arnd Bergmann: "There are two new mystery SoCs with very little public information about them so far, Qualcomm's Cortex-A78C based "Shikra" and Altera's Cortex-A720 based Agilex72 SOCFPGA. We have also gained support for a couple of SoCs from the 2023/2024 timeframe that have been in the making for a while: - The Apple platform gains support for M3 Pro, Max and Ultra SoC, following the basic M3 support from 7.2. - Samsung Exynos 1580 is a high-end mobile phone SoC from 2024 - Canaan K230 is a RISC-V based 64-bit AI SoC, based on the earlier K210 chip - Sophgo SG2000 is a mixed Arm/RISC-V chip that was already supported using the Arm core but is now also added for RISC-V along with several other variants of the cv18xx series In terms of newly added machines we have reference platforms for all the chips above, plus - Only four 32-bit Arm boards: two older phones and two older industrial/embedded boards; using Allwinner, Qualcomm and Rockchip SoCs - Three laptops und three phones using Qualcomm SoCs - Ten 64-bit Rockchips based single-board computers, along with one NAS box and a game console. - Seven industrial/embedded boards and modules using NXP i.MX8/9 SoCs. - A Lenovo desktop box based on NVIDIA Jetson Xavier NX - A few more single-board computers based on Allwinnner A133, Spacemit K1 and TI AM62. As usual, there is a constant stream of minor cleanups and fixes towards addressing the 'dt-check-style --mode strict' warnings, and everyone is expected to address those warnings for new submissions now" * tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (864 commits) Revert "riscv: dts: spacemit: k3: add i2s0-i2s5 nodes" Documentation/process: maintainer-soc: Mention expectation about dt-check-style ARM: dts: helios4: add SATA regulator supplies ARM: dts: helios4: add vcc-supply to GPIO expander ARM: dts: helios4: add vcc-supply to EEPROM arm64: dts: turris-mox: fix usb3 phys arm64: dts: ti: Correct white-space style arm64: dts: ti: k3-am64: Fix MDIO clock reference for ICSSG0 node arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies ... 
Pull SoC devicetree updates from Arnd Bergmann:
 "There are two new mystery SoCs with very little public information
  about them so far, Qualcomm's Cortex-A78C based "Shikra" and Altera's
  Cortex-A720 based Agilex72 SOCFPGA.

  We have also gained support for a couple of SoCs from the 2023/2024
  timeframe that have been in the making for a while:

   - The Apple platform gains support for M3 Pro, Max and Ultra SoC,
     following the basic M3 support from 7.2.

   - Samsung Exynos 1580 is a high-end mobile phone SoC from 2024

   - Canaan K230 is a RISC-V based 64-bit AI SoC, based on the earlier
     K210 chip

   - Sophgo SG2000 is a mixed Arm/RISC-V chip that was already supported
     using the Arm core but is now also added for RISC-V along with
     several other variants of the cv18xx series

  In terms of newly added machines we have reference platforms for all
  the chips above, plus

   - Only four 32-bit Arm boards: two older phones and two older
     industrial/embedded boards; using Allwinner, Qualcomm and Rockchip
     SoCs

   - Three laptops und three phones using Qualcomm SoCs

   - Ten 64-bit Rockchips based single-board computers, along with one
     NAS box and a game console.

   - Seven industrial/embedded boards and modules using NXP i.MX8/9
     SoCs.

   - A Lenovo desktop box based on NVIDIA Jetson Xavier NX

   - A few more single-board computers based on Allwinnner A133,
     Spacemit K1 and TI AM62.

  As usual, there is a constant stream of minor cleanups and fixes
  towards addressing the 'dt-check-style --mode strict' warnings, and
  everyone is expected to address those warnings for new submissions
  now"

* tag 'soc-dt-7.3' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (864 commits)
  Revert "riscv: dts: spacemit: k3: add i2s0-i2s5 nodes"
  Documentation/process: maintainer-soc: Mention expectation about dt-check-style
  ARM: dts: helios4: add SATA regulator supplies
  ARM: dts: helios4: add vcc-supply to GPIO expander
  ARM: dts: helios4: add vcc-supply to EEPROM
  arm64: dts: turris-mox: fix usb3 phys
  arm64: dts: ti: Correct white-space style
  arm64: dts: ti: k3-am64: Fix MDIO clock reference for ICSSG0 node
  arm64: dts: qcom: talos-evk: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sa8155p-adp: Fix swapped USB and UFS QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: eliza-mtp: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: lemans: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: glymur: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: kaanapali: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sar2130p: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8750: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sm8650: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: purwa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: hamoa: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  arm64: dts: qcom: sc8180x: Fix swapped USB QMP PHY vdda-phy/vdda-pll supplies
  ...
dt-bindings: clock: ti,keystone-gate: Convert to DT schema 2026-08-17T16:28:15+00:00 Bhargav Joshi j.bhargav.u@gmail.com 2026-07-25T20:04:08+00:00 368500fcb3679af69b244e394a35be47a799a725 Convert Texas Instruments keystone PSC clock binding to DT schema. The vendor-specific 'domain-id' property is intentionally kept without a "ti," prefix to preserve existing ABI since driver and existing board file use property without "ti," prefix. Also update the reference to this binding in ti,keystone-rproc.txt to point at the new filename. Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Convert Texas Instruments keystone PSC clock binding to DT schema.

The vendor-specific 'domain-id' property is intentionally kept without a
"ti," prefix to preserve existing ABI since driver and existing board
file use property without "ti," prefix.

Also update the reference to this binding in ti,keystone-rproc.txt to
point at the new filename.

Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock: ti: Convert APLL clock to DT schema 2026-08-17T16:28:14+00:00 Eduard Bostina egbostina@gmail.com 2026-07-30T08:30:19+00:00 16f212563f86646a07ca97b334e1c7d97d3ee6fd Convert the Texas Instruments APLL clock bindings to DT schema. Signed-off-by: Eduard Bostina <egbostina@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Convert the Texas Instruments APLL clock bindings to DT schema.

Signed-off-by: Eduard Bostina <egbostina@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock: ti,clockdomain: Convert to DT schema 2026-08-17T16:28:12+00:00 Bhargav Joshi j.bhargav.u@gmail.com 2026-08-10T18:54:59+00:00 3a6deb47cdd47e50b25779ad8321a7aaf20e9d23 Convert TI clockdomain to yaml DT schema. Drop '#clock-cells' from the required list as this binding doesn't define a new clock binding type, it is used to group existing clock nodes under hardware hierarchy. Most existing dts omit '#clock-cells'. Update the reference to the old legacy text binding in the description of bindings/clock/ti/ti,gate-clock.yaml to point to the new YAML file. Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Convert TI clockdomain to yaml DT schema. Drop '#clock-cells' from the
required list as this binding doesn't define a new clock binding type,
it is used to group existing clock nodes under hardware hierarchy. Most
existing dts omit '#clock-cells'.

Update the reference to the old legacy text binding in the description
of bindings/clock/ti/ti,gate-clock.yaml to point to the new YAML file.

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Bhargav Joshi <j.bhargav.u@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
dt-bindings: clock: Correct white-space style 2026-08-17T16:28:10+00:00 Krzysztof Kozlowski krzysztof.kozlowski@oss.qualcomm.com 2026-08-01T19:55:41+00:00 5d7ebde44469086af6c3486e0bbed2d8b5c522f1 Correct a few white-space issues, like double space after '=' or before bracket '{' characters, which will be flagged by dt-check-style. No functional changes. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Reviewed-by: Brian Masney <bmasney@redhat.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Stephen Boyd <sboyd@kernel.org> 
Correct a few white-space issues, like double space after '=' or before
bracket '{' characters, which will be flagged by dt-check-style.  No
functional changes.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>