summaryrefslogtreecommitdiff
path: root/drivers/gpu/nova-core
AgeCommit message (Collapse)Author
2026-01-24gpu: nova-core: rename Imem to ImemSecureTimur Tabi
Rename FalconMem::Imem to ImemSecure to indicate that it references Secure Instruction Memory. This change has no functional impact. On Falcon cores, pages in instruction memory can be tagged as Secure or Non-Secure. For GA102 and later, only Secure is used, which is why FalconMem::Imem seems appropriate. However, Turing firmware images can also contain non-secure sections, and so FalconMem needs to support that. By renaming Imem to ImemSec now, future patches for Turing support will be simpler. Nouveau uses the term "IMEM" to refer both to the Instruction Memory block on Falcon cores as well as to the images of secure firmware uploaded to part of IMEM. OpenRM uses the terms "ImemSec" and "ImemNs" instead, and uses "IMEM" just to refer to the physical memory device. Renaming these terms allows us to align with OpenRM, avoid confusion between IMEM and ImemSec, and makes future patches simpler. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20260122222848.2555890-2-ttabi@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2026-01-23rust: io: separate generic I/O helpers from MMIO implementationZhi Wang
The previous Io<SIZE> type combined both the generic I/O access helpers and MMIO implementation details in a single struct. This coupling prevented reusing the I/O helpers for other backends, such as PCI configuration space. Establish a clean separation between the I/O interface and concrete backends by separating generic I/O helpers from MMIO implementation. Introduce a new trait hierarchy to handle different access capabilities: - IoCapable<T>: A marker trait indicating that a backend supports I/O operations of a certain type (u8, u16, u32, or u64). - Io trait: Defines fallible (try_read8, try_write8, etc.) and infallibile (read8, write8, etc.) I/O methods with runtime bounds checking and compile-time bounds checking. - IoKnownSize trait: The marker trait for types support infallible I/O methods. Move the MMIO-specific logic into a dedicated Mmio<SIZE> type that implements the Io traits. Rename IoRaw to MmioRaw and update consumers to use the new types. Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Alice Ryhl <aliceryhl@google.com> Cc: Bjorn Helgaas <helgaas@kernel.org> Cc: Gary Guo <gary@garyguo.net> Cc: Danilo Krummrich <dakr@kernel.org> Cc: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Zhi Wang <zhiw@nvidia.com> Reviewed-by: Alice Ryhl <aliceryhl@google.com> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Gary Guo <gary@garyguo.net> Link: https://patch.msgid.link/20260121202212.4438-3-zhiw@nvidia.com [ Add #[expect(unused)] to define_{read,write}!(). - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-16Merge tag 'v6.19-rc5' into drm-rust-nextDanilo Krummrich
We need the drm-rust fixes from -rc5 in here for nova-core to build on top of. Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-12gpu: nova-core: add missing newlines to several print stringsTimur Tabi
Although the dev_xx!() macro calls do not technically require terminating newlines for the format strings, they should be added anyway to maintain consistency, both within Rust code and with the C versions. Signed-off-by: Timur Tabi <ttabi@nvidia.com> Reviewed-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260107201647.2490140-2-ttabi@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-12gpu: nova-core: check for overflow to DMATRFBASE1Timur Tabi
The NV_PFALCON_FALCON_DMATRFBASE/1 register pair supports DMA addresses up to 49 bits only, but the write to DMATRFBASE1 could exceed that. To mitigate, check first that the DMA address will fit. Reviewed-by: John Hubbard <jhubbard@nvidia.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Fixes: 69f5cd67ce41 ("gpu: nova-core: add falcon register definitions and base code") Signed-off-by: Timur Tabi <ttabi@nvidia.com> Link: https://patch.msgid.link/20260107201647.2490140-1-ttabi@nvidia.com [ Import ::kernel::dma::DmaMask. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-12gpu: nova-core: don't print raw PMU table entriesJohn Hubbard
Remove the (large) raw form of the PMU table entries. The resulting PMULookupTable is still getting printed (in more useful form) later, anyway, so this was redundant, even for debugging. This output (the example is from an Ampere GPU) is what is being removed: NovaCore 0000:e1:00.0: PMU entry: [01, 01, 54, 54, 01, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [07, 06, e0, b7, 03, 00] NovaCore 0000:e1:00.0: PMU entry: [08, 01, bc, 56, 05, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [45, 07, 88, da, 01, 00] NovaCore 0000:e1:00.0: PMU entry: [85, 07, 34, c9, 02, 00] NovaCore 0000:e1:00.0: PMU entry: [49, 05, 7c, b3, 04, 00] NovaCore 0000:e1:00.0: PMU entry: [89, 05, 1c, 05, 05, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] NovaCore 0000:e1:00.0: PMU entry: [00, 00, 00, 00, 00, 00] And it is immediately followed by a more useful, interpreted list of selected PMU table data, which is *not* being removed as part of this commit. That looks like this: NovaCore 0000:e1:00.0: PmuLookupTableEntry desc: FalconUCodeDescV3 { hdr: 78381825, stored_size: 59904, pkc_data_offset: 1444, interface_offset: 28, imem_phys_base: 0, imem_load_size: 57856, imem_virt_base: 0, dmem_phys_base: 0, dmem_load_size: 2048, engine_id_mask: 1024, ucode_id: 9, signature_count: 3, signature_versions: 7, _reserved: 37449, } Signed-off-by: John Hubbard <jhubbard@nvidia.com> Acked-by: Joel Fernandes <joelagnelf@nvidia.com> Link: https://patch.msgid.link/20260108005811.86014-3-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-12gpu: nova-core: preserve error information in gpu_name()John Hubbard
Change gpu_name() to return a Result instead of an Option. This avoids silently discarding error information when parsing the GPU name string from the GSP. Update the callsite to log a warning with the error details on failure, rather than just displaying "invalid GPU name". Suggested-by: Danilo Krummrich <dakr@kernel.org> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260108005811.86014-2-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-07gpu: nova-core: use CStr::from_bytes_until_nul() in elf64_section()John Hubbard
Instead of open-coding the steps for extracting a null-terminated string, use the newly available CStr::from_bytes_until_nul(). Suggested-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260106035226.48853-3-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2026-01-07gpu: nova-core: use CStr::from_bytes_until_nul() and remove util.rsJohn Hubbard
The util.rs module contained a single helper function, str_from_null_terminated(), which duplicated functionality that is now available in core::ffi::CStr. Specifically, CStr::from_bytes_until_nul() is available in the kernel's minimum supported Rust version (1.78.0), so it time to stop using this custom workaround. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Link: https://patch.msgid.link/20260106035226.48853-2-jhubbard@nvidia.com Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-29gpu: nova-core: gsp: move appropriate code into pin initializerDanilo Krummrich
Relocate the code that technically fits in the pin initializer into the initializer itself. While, thanks to pin_init_scope(), it is also possible to keep it as is, moving appropriate code into the initializer has the advantage that it structures the dependencies of fields naturally. For instance, intermediate data that is only needed for a single field goes into the initializer block of this field, making it obvious that it is not needed by anything else. On the other hand, intermediate data that is needed for multiple fields to initialize remains above the initializer, naturally indicating that it is needed my multiple fields. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Link: https://patch.msgid.link/20251218155239.25243-5-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-29gpu: nova-core: gsp: get rid of redundant Result in Gsp::new()Danilo Krummrich
In Gsp::new(), utilize pin_init_scope() to get rid of the Result in the returned Result<impl PinInit<T, Error>> which is unnecessarily redundant. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Link: https://patch.msgid.link/20251218155239.25243-4-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-29gpu: nova-core: fw: move appropriate code into pin initializerDanilo Krummrich
Relocate the code that technically fits in the pin initializer into the initializer itself. While, thanks to pin_init_scope(), it is also possible to keep it as is, moving appropriate code into the initializer has the advantage that it structures the dependencies of fields naturally. For instance, intermediate data that is only needed for a single field goes into the initializer block of this field, making it obvious that it is not needed by anything else. On the other hand, intermediate data that is needed for multiple fields to initialize remains above the initializer, naturally indicating that it is needed my multiple fields. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Link: https://patch.msgid.link/20251218155239.25243-3-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-29gpu: nova-core: fw: get rid of redundant Result in GspFirmware::new()Danilo Krummrich
In GspFirmware::new(), utilize pin_init_scope() to get rid of the Result in the returned Result<impl PinInit<T, Error>> which is unnecessarily redundant. Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Link: https://patch.msgid.link/20251218155239.25243-2-dakr@kernel.org Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-22gpu: nova: replace `kernel::c_str!` with C-StringsTamir Duberstein
C-String literals were added in Rust 1.77. Replace instances of `kernel::c_str!` with C-String literals where possible. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Reviewed-by: Alice Ryhl <aliceryhl@google.com> Reviewed-by: Benno Lossin <lossin@kernel.org> Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Tamir Duberstein <tamird@gmail.com> Reviewed-by: Daniel Almeida <daniel.almeida@collabora.com> Link: https://patch.msgid.link/20251222-cstr-nova-v1-1-0e2353d5debe@gmail.com [ Use 'nova' commit subject prefix; use kernel vertical import style. - Danilo ] Signed-off-by: Danilo Krummrich <dakr@kernel.org>
2025-12-18drivers: gpu: Update ARef imports from sync::arefShankari Anand
Update call sites to import `ARef` from `sync::aref` instead of `types`. This aligns with the ongoing effort to move `ARef` and `AlwaysRefCounted` to sync. Suggested-by: Benno Lossin <lossin@kernel.org> Link: https://github.com/Rust-for-Linux/linux/issues/1173 Signed-off-by: Shankari Anand <shankari.ak0208@gmail.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Acked-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20251123092438.182251-3-shankari.ak0208@gmail.com [aliceryhl: keep trailing // at last import] Signed-off-by: Alice Ryhl <aliceryhl@google.com>
2025-12-16gpu: nova-core: gsp: replace firmware version with "bindings" aliasAlexandre Courbot
We have an "bindings" alias to avoid having to mention the firmware version again and again, and limit the diff when upgrading the firmware. Use it where we neglected to. Fixes: eaf0989c77e4 ("gpu: nova-core: Add bindings required by GSP sequencer") Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20251216-nova-fixes-v3-4-c7469a71f7c4@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2025-12-16gpu: nova-core: bindings: derive `MaybeZeroable`Alexandre Courbot
Commit 4846300ba8f9 ("rust: derive `Zeroable` for all structs & unions generated by bindgen where possible") automatically derives `MaybeZeroable` for all bindings. This is better than selectively deriving `Zeroable` as it ensures all types that can implement `Zeroable` do. Regenerate the nova-core bindings so they benefit from this, and remove a now unneeded implementation of `Zeroable`. Fixes: 75f6b1de8133 ("gpu: nova-core: gsp: Add GSP command queue bindings and handling") Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20251216-nova-fixes-v3-3-c7469a71f7c4@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2025-12-16gpu: nova-core: gsp: fix length of received messagesAlexandre Courbot
The size of messages' payload is miscalculated, leading to extra data passed to the message handler. While this is not a problem with our current set of commands, others with a variable-length payload may misbehave. Fix this by introducing a method returning the payload size and using it. Fixes: 75f6b1de8133 ("gpu: nova-core: gsp: Add GSP command queue bindings and handling") Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Alistair Popple <apopple@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20251216-nova-fixes-v3-2-c7469a71f7c4@nvidia.com [acourbot@nvidia.com: update `PANIC:` comments as pointed out by Joel.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2025-12-16gpu: nova-core: bindings: add missing explicit paddingAlexandre Courbot
Explicit padding is needed in order to avoid uninitialized bytes and safely implement `AsBytes`. The `--explicit-padding` of bindgen was omitted by mistake when these bindings were generated. Fixes: 13f85988d4fa ("gpu: nova-core: gsp: Retrieve GSP static info to gather GPU information") Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20251216-nova-fixes-v3-1-c7469a71f7c4@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2025-12-16gpu: nova-core: select RUST_FW_LOADER_ABSTRACTIONSAlexandre Courbot
RUST_FW_LOADER_ABSTRACTIONS was depended on by NOVA_CORE, but NOVA_CORE is selected by DRM_NOVA. This creates a situation where, if DRM_NOVA is selected, NOVA_CORE gets enabled but not RUST_FW_LOADER_ABSTRACTIONS, which results in a build error. Since the firmware loader is an implementation detail of the driver, it should be enabled along with it, so change the "depends on" to a "select". Fixes: 54e6baf123fd ("gpu: nova-core: add initial driver stub") Closes: https://lore.kernel.org/oe-kbuild-all/202512061721.rxKGnt5q-lkp@intel.com/ Tested-by: Alyssa Ross <hi@alyssa.is> Acked-by: Danilo Krummrich <dakr@kernel.org> Link: https://patch.msgid.link/20251106-b4-select-rust-fw-v3-2-771172257755@nvidia.com Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
2025-12-05Merge tag 'driver-core-6.19-rc1' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core Pull driver core updates from Danilo Krummrich: "Arch Topology: - Move parse_acpi_topology() from arm64 to common code for reuse in RISC-V CPU: - Expose housekeeping CPUs through /sys/devices/system/cpu/housekeeping - Print a newline (or 0x0A) instead of '(null)' reading /sys/devices/system/cpu/nohz_full when nohz_full= is not set debugfs - Remove (broken) 'no-mount' mode - Remove redundant access mode checks in debugfs_get_tree() and debugfs_create_*() functions Devres: - Remove unused devm_free_percpu() helper - Move devm_alloc_percpu() from device.h to devres.h Firmware Loader: - Replace simple_strtol() with kstrtoint() - Do not call cancel_store() when no upload is in progress kernfs: - Increase struct super_block::maxbytes to MAX_LFS_FILESIZE - Fix a missing unwind path in __kernfs_new_node() Misc: - Increase the name size in struct auxiliary_device_id to 40 characters - Replace system_unbound_wq with system_dfl_wq and add WQ_PERCPU to alloc_workqueue() Platform: - Replace ERR_PTR() with IOMEM_ERR_PTR() in platform ioremap functions Rust: - Auxiliary: - Unregister auxiliary device on parent device unbind - Move parent() to impl Device; implement device context aware parent() for Device<Bound> - Illustrate how to safely obtain a driver's device private data when calling from an auxiliary driver into the parant device driver - DebugFs: - Implement support for binary large objects - Device: - Let probe() return the driver's device private data as pinned initializer, i.e. impl PinInit<Self, Error> - Implement safe accessor for a driver's device private data for Device<Bound> (returned reference can't out-live driver binding and guarantees the correct private data type) - Implement AsBusDevice trait, to be used by class device abstractions to derive the bus device type of the parent device - DMA: - Store raw pointer of allocation as NonNull - Use start_ptr() and start_ptr_mut() to inherit correct mutability of self - FS: - Add file::Offset type alias - I2C: - Add abstractions for I2C device / driver infrastructure - Implement abstractions for manual I2C device registrations - I/O: - Use "kernel vertical" style for imports - Define ResourceSize as resource_size_t - Move ResourceSize to top-level I/O module - Add type alias for phys_addr_t - Implement Rust version of read_poll_timeout_atomic() - PCI: - Use "kernel vertical" style for imports - Move I/O and IRQ infrastructure to separate files - Add support for PCI interrupt vectors - Implement TryInto<IrqRequest<'a>> for IrqVector<'a> to convert an IrqVector bound to specific pci::Device into an IrqRequest bound to the same pci::Device's parent Device - Leverage pin_init_scope() to get rid of redundant Result in IRQ methods - PinInit: - Add {pin_}init_scope() to execute code before creating an initializer - Platform: - Leverage pin_init_scope() to get rid of redundant Result in IRQ methods - Timekeeping: - Implement abstraction of udelay() - Uaccess: - Implement read_slice_partial() and read_slice_file() for UserSliceReader - Implement write_slice_partial() and write_slice_file() for UserSliceWriter sysfs: - Prepare the constification of struct attribute" * tag 'driver-core-6.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/driver-core/driver-core: (75 commits) rust: pci: fix build failure when CONFIG_PCI_MSI is disabled debugfs: Fix default access mode config check debugfs: Remove broken no-mount mode debugfs: Remove redundant access mode checks driver core: Check drivers_autoprobe for all added devices driver core: WQ_PERCPU added to alloc_workqueue users driver core: replace use of system_unbound_wq with system_dfl_wq tick/nohz: Expose housekeeping CPUs in sysfs tick/nohz: avoid showing '(null)' if nohz_full= not set sysfs/cpu: Use DEVICE_ATTR_RO for nohz_full attribute kernfs: fix memory leak of kernfs_iattrs in __kernfs_new_node fs/kernfs: raise sb->maxbytes to MAX_LFS_FILESIZE mod_devicetable: Bump auxiliary_device_id name size sysfs: simplify attribute definition macros samples/kobject: constify 'struct foo_attribute' samples/kobject: add is_visible() callback to attribute group sysfs: attribute_group: enable const variants of is_visible() sysfs: introduce __SYSFS_FUNCTION_ALTERNATIVE() sysfs: transparently handle const pointers in ATTRIBUTE_GROUPS() sysfs: attribute_group: allow registration of const attribute ...
2025-11-17gpu: nova-core: make formatting compatible with rust treeAlice Ryhl
Commit 38b7cc448a5b ("gpu: nova-core: implement Display for Spec") in drm-rust-next introduced some usage of the Display trait, but the Display trait is being modified in the rust tree this cycle. Thus, to avoid conflicts with the Rust tree, tweak how the formatting machinery is used in a way where it works both with and without the changes in the Rust tree. Reviewed-by: Alexandre Courbot <acourbot@nvidia.com> Tested-by: Alexandre Courbot <acourbot@nvidia.com> Link: https://patch.msgid.link/20251117-nova-fmt-rust-v1-1-651ca28cd98f@google.com Signed-off-by: Alice Ryhl <aliceryhl@google.com>
2025-11-15gpu: nova-core: provide a clear error report for unsupported GPUsJohn Hubbard
Pass in a PCI device to Spec::new(), and provide a Display implementation for boot42, in order to provide a clear, concise report of what happened: the driver read NV_PMC_BOOT42, and found that the GPU is not supported. For very old GPUs (older than Fermi), the driver still returns ENODEV, but it does so without a driver-specific dmesg report. That is exactly appropriate, because if such a GPU is installed, it can only be supported by Nouveau. And if so, the user is not helped by additional error messages from Nova. Here's the full dmesg output for a Blackwell (not yet supported) GPU: NovaCore 0000:01:00.0: Probe Nova Core GPU driver. NovaCore 0000:01:00.0: Unsupported chipset: boot42 = 0x1b2a1000 (architecture 0x1b, implementation 0x2) NovaCore 0000:01:00.0: probe with driver NovaCore failed with error -524 Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Danilo Krummrich <dakr@kernel.org> Cc: Timur Tabi <ttabi@nvidia.com> Cc: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> [acourbot@nvidia.com: fix commit log with ENODEV (not ENOTSUPP) error code for unsupported GPUs.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251115010923.1192144-5-jhubbard@nvidia.com>
2025-11-15gpu: nova-core: add boot42 support for next-gen GPUsJohn Hubbard
NVIDIA GPUs are moving away from using NV_PMC_BOOT_0 to contain architecture and revision details, and will instead use NV_PMC_BOOT_42 in the future. NV_PMC_BOOT_0 will contain a specific set of values that will mean "go read NV_PMC_BOOT_42 instead". Change the selection logic in Nova so that it will claim Turing and later GPUs. This will work for the foreseeable future, without any further code changes here, because all NVIDIA GPUs are considered, from the oldest supported on Linux (NV04), through the future GPUs. Add some comment documentation to explain, chronologically, how boot0 and boot42 change with the GPU eras, and how that affects the selection logic. Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Danilo Krummrich <dakr@kernel.org> Cc: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> [acourbot@nvidia.com: remove unneeded `From<BOOT_0> for Revision` implementation.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251115010923.1192144-4-jhubbard@nvidia.com>
2025-11-15gpu: nova-core: make Architecture behave as a u8 typeJohn Hubbard
This allows Architecture to be passed into register!() and bitfield!() macro calls. That in turn requires a default implementation for Architecture. This simplifies transforming BOOT0 (and later, BOOT42) register values into GPU architectures. Cc: Danilo Krummrich <dakr@kernel.org> Cc: Timur Tabi <ttabi@nvidia.com> Suggested-by: Alexandre Courbot <acourbot@nvidia.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251115010923.1192144-3-jhubbard@nvidia.com>
2025-11-15gpu: nova-core: prepare Spec and Revision types for boot0/boot42John Hubbard
Allow a both Revision and Spec to be constructed directly from a NV_PMC_BOOT_0 register. Also, slightly enhance the comment about Spec, to be more precise. Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Danilo Krummrich <dakr@kernel.org> Cc: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251115010923.1192144-2-jhubbard@nvidia.com>
2025-11-15gpu: nova-core: gsp: Retrieve GSP static info to gather GPU informationAlistair Popple
After GSP initialization is complete, retrieve the static configuration information from GSP-RM. This information includes GPU name, capabilities, memory configuration, and other properties. On some GPU variants, it is also required to do this for initialization to complete. Signed-off-by: Alistair Popple <apopple@nvidia.com> Co-developed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [acourbot@nvidia.com: properly abstract the command's bindings, add relevant methods, make str_from_null_terminated return an Option, fix size of GPU name array.] Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-14-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: gsp: Wait for gsp initialization to completeAlistair Popple
This adds the GSP init done command to wait for GSP initialization to complete. Once this command has been received the GSP is fully operational and will respond properly to normal RPC commands. Signed-off-by: Alistair Popple <apopple@nvidia.com> Co-developed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> [acourbot@nvidia.com: move new definitions to end of commands.rs, rename to `wait_gsp_init_done` and remove timeout argument.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-13-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: sequencer: Implement core resume operationJoel Fernandes
Implement core resume operation. This is the last step of the sequencer resulting in resume of the GSP and proceeding to INIT_DONE stage of GSP boot. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-12-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: sequencer: Implement basic core operationsJoel Fernandes
These opcodes implement various falcon-related boot operations: reset, start, wait-for-halt. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-11-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: sequencer: Add delay opcode supportJoel Fernandes
Implement a sequencer opcode for delay operations. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-10-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: sequencer: Add register opcodesJoel Fernandes
These opcodes are used for register write, modify, poll and store (save) sequencer operations. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> [acourbot@nvidia.com: apply Lyude's suggested fixes.] Message-ID: <20251114195552.739371-9-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: Implement the GSP sequencerJoel Fernandes
Implement the GSP sequencer which culminates in INIT_DONE message being received from the GSP indicating that the GSP has successfully booted. This is just initial sequencer support, the actual commands will be added in the next patches. Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [acourbot@nvidia.com: move GspSequencerInfo definition before its impl blocks and rename it to GspSequence, adapt imports in sequencer.rs to new formatting rules, remove `timeout` argument to harmonize with other commands.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-8-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: Add bindings required by GSP sequencerJoel Fernandes
Add several firmware bindings required by GSP sequencer code. Co-developed-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alistair Popple <apopple@nvidia.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [acourbot@nvidia.com: remove a couple stray lines/unwanted comment changes.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-7-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: gsp: Add support for checking if GSP reloadedJoel Fernandes
During the sequencer process, we need to check if GSP was successfully reloaded. Add functionality to check for the same. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-6-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: falcon: Move dma_reset functionality into helperJoel Fernandes
Move dma_reset so we can use it for the upcoming sequencer functionality. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-5-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: falcon: Move mbox functionalities into helperJoel Fernandes
Move falcon reading/writing to mbox functionality into helper so we can use it from the sequencer resume flow. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> [acourbot@nvidia.com: make write/read mailbox methods unfallible.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-4-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: falcon: Move start functionality into separate helperJoel Fernandes
Move start functionality into a separate helper so we can use it from the sequencer. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-3-joelagnelf@nvidia.com>
2025-11-15gpu: nova-core: falcon: Move waiting until halted to a helperJoel Fernandes
Move the "waiting until halted" functionality into a helper so that we can use it in the sequencer, which is a separate sequencer operation. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114195552.739371-2-joelagnelf@nvidia.com>
2025-11-14gpu: nova-core: implement Display for SpecJohn Hubbard
Implement Display for Spec. This simplifies the dev_info!() code for printing banners such as: NVIDIA (Chipset: GA104, Architecture: Ampere, Revision: a.1) Cc: Alexandre Courbot <acourbot@nvidia.com> Cc: Danilo Krummrich <dakr@kernel.org> Cc: Timur Tabi <ttabi@nvidia.com> Reviewed-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: John Hubbard <jhubbard@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251114024109.465136-2-jhubbard@nvidia.com>
2025-11-14gpu: nova-core: gsp: Boot GSPAlistair Popple
Boot the GSP to the RISC-V active state. Completing the boot requires running the CPU sequencer which will be added in a future commit. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-15-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: falcon: Add support to write firmware versionJoel Fernandes
This will be needed by both the GSP boot code as well as GSP resume code in the sequencer. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-14-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: falcon: Add support to check if RISC-V is activeJoel Fernandes
Add definition for RISCV_CPUCTL register and use it in a new falcon API to check if the RISC-V core of a Falcon is active. It is required by the sequencer to know if the GSP's RISCV processor is active. Reviewed-by: Lyude Paul <lyude@redhat.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-13-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: gsp: Add SetRegistry commandAlistair Popple
Add support for sending the SetRegistry command, which is critical to GSP initialization. The RM registry is serialized into a packed format and sent via the command queue. For now only three parameters which are required to boot GSP are hardcoded. In the future a kernel module parameter will be added to enable other parameters to be added. Signed-off-by: Alistair Popple <apopple@nvidia.com> [acourbot@nvidia.com: split into its own patch.] Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-12-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: gsp: Add SetSystemInfo commandAlistair Popple
Add support for sending the SetSystemInfo command, which provides required hardware information to the GSP and is critical to its initialization. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-11-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: gsp: Create rmargsAlistair Popple
Initialise the GSP resource manager arguments (rmargs) which provides initialisation parameters to the GSP firmware during boot. The rmargs structure contains arguments to configure the GSP message/command queue location. These are mapped for coherent DMA and added to the libos data structure for access when booting GSP. Signed-off-by: Alistair Popple <apopple@nvidia.com> Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-10-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: gsp: Add GSP command queue bindings and handlingAlistair Popple
This commit introduces core infrastructure for handling GSP command and message queues in the nova-core driver. The command queue system enables bidirectional communication between the host driver and GSP firmware through a remote message passing interface. The interface is based on passing serialised data structures over a ring buffer with separate transmit and receive queues. Commands are sent by writing to the CPU transmit queue and waiting for completion via the receive queue. To ensure safety mutable or immutable (depending on whether it is a send or receive operation) references are taken on the command queue when allocating the message to write/read to. This ensures message memory remains valid and the command queue can't be mutated whilst an operation is in progress. Currently this is only used by the probe() routine and therefore can only used by a single thread of execution. Locking to enable safe access from multiple threads will be introduced in a future series when that becomes necessary. Signed-off-by: Alistair Popple <apopple@nvidia.com> Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-9-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: Add zeroable trait to bindingsAlistair Popple
Derive the Zeroable trait for existing bindgen generated bindings. This is safe because all bindgen generated types are simple integer types for which any bit pattern, including all zeros, is valid. Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-7-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: Add a slice-buffer (sbuffer) datastructureJoel Fernandes
A data structure that can be used to write across multiple slices which may be out of order in memory. This lets SBuffer user correctly and safely write out of memory order, without error-prone tracking of pointers/offsets. let mut buf1 = [0u8; 3]; let mut buf2 = [0u8; 5]; let mut sbuffer = SBuffer::new([&mut buf1[..], &mut buf2[..]]); let data = b"hello"; let result = sbuffer.write(data); Reviewed-by: Lyude Paul <lyude@redhat.com> Co-developed-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Alistair Popple <apopple@nvidia.com> Signed-off-by: Joel Fernandes <joelagnelf@nvidia.com> Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-6-8ae4058e3c0e@nvidia.com>
2025-11-14gpu: nova-core: gsp: Create wpr metadataAlistair Popple
The GSP requires some pieces of metadata to boot. These are passed in a struct which the GSP transfers via DMA. Create this struct and get a handle to it for future use when booting the GSP. Signed-off-by: Alistair Popple <apopple@nvidia.com> Co-developed-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Message-ID: <20251110-gsp_boot-v9-5-8ae4058e3c0e@nvidia.com>
generated by cgit v1.2.3 (git 2.25.1) at 2026-06-04 13:36:43 +0000