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path: root/drivers/gpu/drm/amd/amdgpu
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2025-12-10drm/amdgpu: Enable atomics for all the available xccHawking Zhang
Apply TCP_UTCL0_CNTL1 settings to all the available xcc Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Update MES VM_CNTX_CNTL for XNACK off for GFX 12.1Mukul Joshi
Currently, we do not turn off retry faults in VM_CONTEXT_CNTL value when passing it to MES if XNACK is off. This creates a situation where XNACK is disabled in SQ but enabled in UTCL2, which is not recommended. As a result, turn off/on retry faults in both SQ and UTCL2 when passing vm_context_cntl value to MES if XNACK is disabled/enabled. Suggested-by: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: Enable per-process XNACK for GFX 12.1.0Mukul Joshi
GFX 12.1.0 will support enabling/disabling XNACK on a per- process basis. This change enables the per process XNACK feature. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Enable retry faults for GFX 12.1Mukul Joshi
Enable retry faults in both GCVM/MMVM Context1 Control and L2_PROTECTION_FAULT_CNTL2 registers for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add IH node-id to XCC mappingMukul Joshi
Add a generic function to map IH node-id to XCC instance. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add interrupt handler for GFX 12.1.0Mukul Joshi
Add a separate interrupt handler for handling interrupts, both retry and no-retry, for GFX 12.1.0. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add UTCL2 Retry fault interrupt for GFX 12.1Mukul Joshi
Add the UTCL2 retry fault interrupt for both GCVM and MMVM for GFX 12.1. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/sdma: add query for CSA size and alignmentAlex Deucher
Needed to query the CSA size and alignment for SDMA user queues. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: fix mes packet params issue when flush hdp.chong li
v4: use func "amdgpu_gfx_get_hdp_flush_mask" to get ref_and_mask for gfx9 through gfx12. v3: Unify the get_ref_and_mask function in amdgpu_gfx_funcs, to support both GFX11 and earlier generations v2: place "get_ref_and_mask" in amdgpu_gfx_funcs instead of amdgpu_ring, since this function only assigns the cp entry. v1: both gfx ring and mes ring use cp0 to flush hdp, cause conflict. use function get_ref_and_mask to assign the cp entry. reassign mes to use cp8 instead. Signed-off-by: chong li <chongli2@amd.com> Acked-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/gfx: add eop size and alignment to shadow infoAlex Deucher
This is used by firmware for compute user queues. Reviewed-by: Prike Liang <Prike.Liang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: update sdma configuration for soc v1_0Likun Gao
Update SDMA instances/masks according to xcc num for multi-xcc models on soc v1.0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Initialize xcp manager for soc v1_0Hawking Zhang
Initialize xcp manager for soc v1_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add soc_v1_0_xcp_funcsHawking Zhang
Implement xcp mgr callbacks for soc v1_0 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Export sdma_v7_1_xcp_funcsHawking Zhang
To be used by soc v1_0 xcp manager Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Export gfx_v12_1_xcp_funcHawking Zhang
To be used by soc v1_0 xcp manager Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add vram_type to ras init_flagsCandice Li
Add vram_type to ras init_flags. Signed-off-by: Candice Li <candice.li@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Add switch_compute_partition callback for imu v12_1Hawking Zhang
To enable switching compute partition mode v2: cleanup (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Implement gfx_v12_1_get_xccs_per_xcpHawking Zhang
Use gfx v12_1 callback to query the numbers of xccs per xcp v2: add todo (Alex) Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Remove redundant check for async_gfx_ringHawking Zhang
Remove the redundant check for async_gfx_ring, as it is not required for gfx v12_1 Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: disable graphics doorbell range for gfx v12_1Likun Gao
Disable doorbell range for graphics engine on gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: enable unmap doorbell handle for gfx v12_1Likun Gao
Enable unmapped doorbell handling for gfx v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: revision doorbel range for gfx v12_1Likun Gao
Revision doorbell range on muti-XCC mode for gfx v12_1. Clean up doorbell range set for graphics engine. V2: Remove doorbell range set from gfx_v12_1_xcc_kiq_init_register. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdkfd: disable shader message vgpr deallocation on gc 12.1Jonathan Kim
Shader messages to deallocate VGPRs prior to shader end can prevent the trap handler from saving context, making debugging and core dumps unreliable. VGPR deallocations for performance gain is negligible. GC 12.1 will NOP shader VGPR deallocation messages via HW settings on driver boot. Signed-off-by: Jonathan Kim <jonathan.kim@amd.com> Acked-by: Harish Kasiviswanathan <harish.kasiviswanathan@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu: Remove redundant pmfw backdoor loadingHawking Zhang
PMFW is integrated into ifwi for gfx 12_1 adapter, making PMFW backdoor loading unnecessary. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Likun Gao <Likun.Gao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amd: Fix unbind/rebind for VCN 4.0.5Mario Limonciello (AMD)
Unbinding amdgpu has no problems, but binding it again leads to an error of sysfs file already existing. This is because it wasn't actually cleaned up on unbind. Add the missing cleanup step. Fixes: 547aad32edac ("drm/amdgpu: add VCN4 ip block support") Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-10drm/amdgpu/acpi: Reduce amdgpu_acpi_detect stack usageSrinivasan Shanmugam
amdgpu_acpi_detect() calls some helper functions it calls have large local structures. When the compiler inlines these helpers, their local data adds to the amdgpu_acpi_detect() stack frame. Mark the helpers with noinline_for_stack: - amdgpu_atif_verify_interface() - amdgpu_atif_get_notification_params() - amdgpu_atif_query_backlight_caps() - amdgpu_atcs_verify_interface() - amdgpu_acpi_enumerate_xcc() This keeps the large temporary objects inside the helper’s own stack frame instead of being inlined into the caller, preventing the caller from growing beyond the stack limit. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:1403:6: warning: stack frame size (1688) exceeds limit (1024) in 'amdgpu_acpi_detect' [-Wframe-larger-than] Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: don't attach the tlb fence for SIAlex Deucher
SI hardware doesn't support pasids, user mode queues, or KIQ/MES so there is no need for this. Doing so results in a segfault as these callbacks are non-existent for SI. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4744 Fixes: f3854e04b708 ("drm/amdgpu: attach tlb fence to the PTs update") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> (cherry picked from commit 820b3d376e8a102c6aeab737ec6edebbbb710e04)
2025-12-08drm/amdgpu: pass the entity to use to ttm public functionsPierre-Eric Pelloux-Prayer
This way the caller can select the one it wants to use. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: pass the entity to use to amdgpu_ttm_map_bufferPierre-Eric Pelloux-Prayer
This way the caller can select the one it wants to use. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: fix error handling in amdgpu_copy_bufferPierre-Eric Pelloux-Prayer
drm_sched_job_add_resv_dependencies can fail in amdgpu_ttm_prepare_job. In this case we need to use amdgpu_job_free to release memory. --- v4: moved job pointer clearing to a different patchset --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: add amdgpu_ttm_job_submit helperPierre-Eric Pelloux-Prayer
Deduplicate the IB padding code and will also be used later to check locking. Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: introduce amdgpu_ttm_buffer_entityPierre-Eric Pelloux-Prayer
No functional change for now, but this struct will have more fields added in the next commit. This change would introduce synchronisation issue, because dependencies between successive jobs are not taken care of properly. For instance, amdgpu_ttm_clear_buffer uses amdgpu_ttm_map_buffer then amdgpu_ttm_fill_mem which should use different entities (default_entity then move/clear entity). To prevent failures for this commit, we limit ourselves to 2 entities: default_entity (which replaces high_pr usages) and clear_entity (which replaces low_pr usages). The next commits will deal with these dependencies correctly, and then we'll be able to use move_entity. --- v2: renamed amdgpu_ttm_buffer_entity v4: don't use move_entity in ttm yet --- Signed-off-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> Reviewed-by: Christian König <christian.koenig@amd.com> (v3) Acked-by: Felix Kuehling <felix.kuehling@amd.com> (v3) Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: add imu support for gc 12_1Likun Gao
Add IMU support for gc version 12.1.0. Only support imu fw loading for imu 12.1.0. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: fix mes code error for muti-xccLikun Gao
Fix some code error for muti-xcc on mes v12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu/gmc12: set MMHUBs based on aid_maskLikun Gao
Update number of mmhub and mid_mask via reuse aid_mask. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Le Ma <le.ma@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: set gfxhub according xcc_mask for gfx 12_1Likun Gao
Set GFXHUB accodring to xcc_mask for gfx version 12_1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: add xcc info for compute ring nameLikun Gao
Add XCC id info for compute ring name on gfx version 12.1. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Revert retry based thrashing prevention on GFX 12.1.0Mukul Joshi
Revert the change to enable retry based thrashing prevention on GFX 12.1.0 for now as its causing data mismatch and slowness issues with multiple HIP tests. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Init single mes instance if xcc_mask is unsetHawking Zhang
Configure a single mes instance if the xcc_mask remains uninitialized. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Setup MTYPEs for GFX 12.1.0Mukul Joshi
For GFX 12.1.0, setup correct MTYPE for a BO depending on its current location relative to the mapping GPU. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Harish Kasiviswanathan <Harish.Kasiviswanathan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: update sh mem base offsets for gfx 12.1Alex Sierra
Signed-off-by: Alex Sierra <alex.sierra@amd.com> Reviewed-by: Philip Yang <Philip.Yang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: Fix SHMEM alignment mode for GFX 12.1.0Mukul Joshi
Alignment mode in SHMEM config register is only a single bit value on GFX 12.1.0 instead of 2 bits in previous asics. Add a new enum and use the correct value of SHMEM alignment mode when programming the SHMEM config register. Signed-off-by: Mukul Joshi <mukul.joshi@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: don't attach the tlb fence for SIAlex Deucher
SI hardware doesn't support pasids, user mode queues, or KIQ/MES so there is no need for this. Doing so results in a segfault as these callbacks are non-existent for SI. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4744 Fixes: f3854e04b708 ("drm/amdgpu: attach tlb fence to the PTs update") Reviewed-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu/sdma_v7_1: Add missing inst_mask entry in sdma_v7_1_inst_gfx_resume()Srinivasan Shanmugam
The comment for sdma_v7_1_inst_gfx_resume() did not include the inst_mask parameter, even though the function takes it as an argument. Update the comment to document inst_mask as the mask of SDMA engine instances to be enabled. Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/sdma_v7_1.c:644 function parameter 'inst_mask' not described in 'sdma_v7_1_inst_gfx_resume' Cc: Likun Gao <Likun.Gao@amd.com> Cc: Le Ma <le.ma@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: Christian König <christian.koenig@amd.com> Signed-off-by: Srinivasan Shanmugam <srinivasan.shanmugam@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: add a helper for processing recoverable GPUVM faultsAlex Deucher
Add a common helper to remove the repeated logic from each gmc module. Suggested-by: Lijo Lazar <lijo.lazar@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu: add soc config init for GC v12_1Likun Gao
Add function to initialize soc configuration information for GC 12.1.0 ASICs. Use it to map IPs and other SOC related information once IP configuration information is available through discovery. Signed-off-by: Likun Gao <Likun.Gao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08amdkfd: fence handler evict and restore a kfd process by its context idZhu Lingshan
In fence enable signaling handler, kfd evicts and restores the corresponding kfd_process, this commit helps find the kfd_process by both its mm and context id. Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08amdkfd: record kfd context id in amdkfd_fenceZhu Lingshan
This commit records the context id of the cooresponding kfd process in amdkfd_fence Signed-off-by: Zhu Lingshan <lingshan.zhu@amd.com> Reviewed-by: Felix Kuehling <felix.kuehling@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu/mes12_1: set multi-xcc mes log addressMichael Chen
Set mes event log address based on xcc id and pipe. Signed-off-by: Michael Chen <michael.chen@amd.com> Reviewed-by: Jack Xiao <Jack.Xiao@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amdgpu/mes12_1: add cooperative dispatch supportJack Xiao
Add initial cooperative dispatch MES support. a. set shared cmd buffer for the group of cooperative dispatch mes. b. automatically dispatch add_hw_queue/remove_hw_queue to master mes. Signed-off-by: Jack Xiao <Jack.Xiao@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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