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2026-01-03arm64: dts: qcom: sm8650: Add description of MCLK pinsVladimir Zapolskiy
Add fixed MCLK pin descriptions for all pins with such supported function. Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20251204041505.131891-3-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: sm8650: Add CAMSS device tree nodeVladimir Zapolskiy
Add Qualcomm SM8650 CAMSS device tree node to the platform dtsi file, the SM8650 CAMSS IP contains * 6 x CSIPHY, * 3 x CSID, 2 x CSID Lite, * 3 x IFE, 2 x IFE Lite. Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on SM8650-QRD Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Link: https://lore.kernel.org/r/20251204041505.131891-2-vladimir.zapolskiy@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: qcs8300: Enable TSENS support for QCS8300 SoCGaurav Kohli
Add TSENS and thermal devicetree node for QCS8300 SoC. Signed-off-by: Gaurav Kohli <quic_gkohli@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822042316.1762153-3-quic_gkohli@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: add hdmi bridge with enable pinJens Glathe
Add TLMM 120 for hdmi bridge enable. In general this is the same setup as on the T14s. Since its using simple-bridge and also is Lenovo, we also use the same realtek,rtd2171 compatible. The real chip identity is not known yet. The bridge is wired with un-swapped lanes, though. Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Link: https://lore.kernel.org/r/20260103-tb16-hdmi-v2-2-92b0930fa82e@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: x1p42100-lenovo-thinkbook-16: force usb2-only mode on ↵Jens Glathe
usb_1_ss2_dwc3 The usb_1_ss2 complex has 2 phys, usb_1_ss2_hsphy and usb_1_ss2_qmpphy. On this laptop, they are used for different peripherals: The hsphy for the fingerprint reader, the qmpphy to drive a hdmi bridge. The normal logical wiring for the dwc3 controller is to both phys. Delete the port@1 to the qmpphy. Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260103-tb16-hdmi-v2-1-92b0930fa82e@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-03arm64: dts: qcom: hamoa: Extend the gcc input clock listTaniya Das
The recent dt-bindings were updated for the missing RX/TX symbol clocks for UFS. Extend the existing list to make sure the DT contains the expected amount of 'clocks' entries. Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Link: https://lore.kernel.org/r/20260103-ufs_symbol_clk-v2-3-51828cc76236@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2026-01-02Merge tag 'x86-urgent-2026-01-02' of ↵Linus Torvalds
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull x86 fix from Ingo Molnar: "Fix the AMD microcode Entrysign signature checking code to include more models" * tag 'x86-urgent-2026-01-02' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: x86/microcode/AMD: Fix Entrysign revision check for Zen5/Strix Halo
2026-01-02s390/ap: Fix typo in function name referenceJulia Lawall
Add missing s into ap_intructions_available. Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr> Reviewed-by: Jimmy Brisson <jbrisson@linux.ibm.com> Signed-off-by: Heiko Carstens <hca@linux.ibm.com>
2026-01-01arm64: dts: arm: Use hyphen in node namesKrzysztof Kozlowski
DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Acked-by: Vincenzo Frascino <vincenzo.frascino@arm.com> Message-Id: <20251223152457.155392-3-krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2026-01-01x86/kvm: Avoid freeing stack-allocated node in kvm_async_pf_queue_taskRyosuke Yasuoka
kvm_async_pf_queue_task() can incorrectly try to kfree() a node allocated on the stack of kvm_async_pf_task_wait_schedule(). This occurs when a task requests a PF while another task's PF request with the same token is still pending. Since the token is derived from the (u32)address in exc_page_fault(), two different tasks can generate the same token. Currently, kvm_async_pf_queue_task() assumes that any entry found in the list is a dummy entry and tries to kfree() it. To fix this, add a flag to the node structure to distinguish stack-allocated nodes, and only kfree() the node if it is a dummy entry. Signed-off-by: Ryosuke Yasuoka <ryasuoka@redhat.com> Message-ID: <20251206140939.144038-1-ryasuoka@redhat.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2025-12-31x86/sev: Carve out the SVSM code into a separate compilation unitBorislav Petkov (AMD)
Move the SVSM-related machinery into a separate compilation unit in order to keep sev/core.c slim and "on-topic". No functional changes. Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20251204124809.31783-4-bp@kernel.org
2025-12-31x86/sev: Add internal header guardsBorislav Petkov (AMD)
All headers need guards ifdeffery. Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://patch.msgid.link/20251204124809.31783-3-bp@kernel.org
2025-12-31x86/sev: Move the internal headerBorislav Petkov (AMD)
Move the internal header out of the usual include/asm/ include path because having an "internal" header there doesn't really make it internal - quite the opposite - that's the normal arch include path. So move where it belongs and make it really internal. No functional changes. Reviewed-by: Tom Lendacky <thomas.lendacky@amd.com> Signed-off-by: Borislav Petkov (AMD) <bp@alien8.de> Link: https://lore.kernel.org/r/20251204145716.GDaTGhTEHNOtSdTkEe@fat_crate.local
2025-12-31LoongArch: BPF: Enhance the bpf_arch_text_poke() functionChenghao Duan
Enhance the bpf_arch_text_poke() function to enable accurate location of BPF program entry points. When modifying the entry point of a BPF program, skip the "move t0, ra" instruction to ensure the correct logic and copy of the jump address. Cc: stable@vger.kernel.org Fixes: 677e6123e3d2 ("LoongArch: BPF: Disable trampoline for kernel module function trace") Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: BPF: Enable trampoline-based tracing for module functionsChenghao Duan
Remove the previous restrictions that blocked the tracing of kernel module functions. Fix the issue that previously caused kernel lockups when attempting to trace module functions. Before entering the trampoline code, the return address register ra shall store the address of the next assembly instruction after the 'bl trampoline' instruction, which is the traced function address, and the register t0 shall store the parent function return address. Refine the trampoline return logic to ensure that register data remains correct when returning to both the traced function and the parent function. Before this patch was applied, the module_attach test in selftests/bpf encountered a deadlock issue. This was caused by an incorrect jump address after the trampoline execution, which resulted in an infinite loop within the module function. Cc: stable@vger.kernel.org Fixes: 677e6123e3d2 ("LoongArch: BPF: Disable trampoline for kernel module function trace") Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: BPF: Adjust the jump offset of tail callsChenghao Duan
Call the next bpf prog and skip the first instruction of TCC initialization. A total of 7 instructions are skipped: 'move t0, ra' 1 inst 'move_imm + jirl' 5 inst 'addid REG_TCC, zero, 0' 1 inst Relevant test cases: the tailcalls test item in selftests/bpf. Cc: stable@vger.kernel.org Fixes: 677e6123e3d2 ("LoongArch: BPF: Disable trampoline for kernel module function trace") Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: BPF: Save return address register ra to t0 before trampolineChenghao Duan
Modify the build_prologue() function to ensure the return address register ra is saved to t0 before entering trampoline operations. This change ensures the accurate return address handling when a BPF program calls another BPF program, preventing errors in the BPF-to-BPF call chain. Cc: stable@vger.kernel.org Fixes: 677e6123e3d2 ("LoongArch: BPF: Disable trampoline for kernel module function trace") Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: BPF: Zero-extend bpf_tail_call() indexHengqi Chen
The bpf_tail_call() index should be treated as a u32 value. Let's zero-extend it to avoid calling wrong BPF progs. See similar fixes for x86 [1]) and arm64 ([2]) for more details. [1]: https://github.com/torvalds/linux/commit/90caccdd8cc0215705f18b92771b449b01e2474a [2]: https://github.com/torvalds/linux/commit/16338a9b3ac30740d49f5dfed81bac0ffa53b9c7 Cc: stable@vger.kernel.org Fixes: 5dc615520c4d ("LoongArch: Add BPF JIT support") Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: BPF: Sign extend kfunc call argumentsHengqi Chen
The kfunc calls are native calls so they should follow LoongArch calling conventions. Sign extend its arguments properly to avoid kernel panic. This is done by adding a new emit_abi_ext() helper. The emit_abi_ext() helper performs extension in place meaning a value already store in the target register (Note: this is different from the existing sign_extend() helper and thus we can't reuse it). Cc: stable@vger.kernel.org Fixes: 5dc615520c4d ("LoongArch: Add BPF JIT support") Signed-off-by: Hengqi Chen <hengqi.chen@gmail.com> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Refactor register restoration in ftrace_common_returnChenghao Duan
Refactor the register restoration sequence in the ftrace_common_return function to clearly distinguish between the logic of normal returns and direct call returns in function tracing scenarios. The logic is as follows: 1. In the case of a normal return, the execution flow returns to the traced function, and ftrace must ensure that the register data is consistent with the state when the function was entered. ra = parent return address; t0 = traced function return address. 2. In the case of a direct call return, the execution flow jumps to the custom trampoline function, and ftrace must ensure that the register data is consistent with the state when ftrace was entered. ra = traced function return address; t0 = parent return address. Cc: stable@vger.kernel.org Fixes: 9cdc3b6a299c ("LoongArch: ftrace: Add direct call support") Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Enable exception fixup for specific ADE subcodeChenghao Duan
This patch allows the LoongArch BPF JIT to handle recoverable memory access errors generated by BPF_PROBE_MEM* instructions. When a BPF program performs memory access operations, the instructions it executes may trigger ADEM exceptions. The kernel’s built-in BPF exception table mechanism (EX_TYPE_BPF) will generate corresponding exception fixup entries in the JIT compilation phase; however, the architecture-specific trap handling function needs to proactively call the common fixup routine to achieve exception recovery. do_ade(): fix EX_TYPE_BPF memory access exceptions for BPF programs, ensure safe execution. Relevant test cases: illegal address access tests in module_attach and subprogs_extable of selftests/bpf. Signed-off-by: Chenghao Duan <duanchenghao@kylinos.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Remove unnecessary checks for ORC unwinderTiezhu Yang
According to the following function definitions, __kernel_text_address() already checks __module_text_address(), so it should remove the check of __module_text_address() in bt_address() at least. int __kernel_text_address(unsigned long addr) { if (kernel_text_address(addr)) return 1; ... return 0; } int kernel_text_address(unsigned long addr) { bool no_rcu; int ret = 1; ... if (is_module_text_address(addr)) goto out; ... return ret; } bool is_module_text_address(unsigned long addr) { guard(rcu)(); return __module_text_address(addr) != NULL; } Furthermore, there are two checks of __kernel_text_address(), one is in bt_address() and the other is after calling bt_address(), it looks like redundant. Handle the exception address first and then use __kernel_text_address() to validate the calculated address for exception or the normal address in bt_address(), then it can remove the check of __kernel_text_address() after calling bt_address(). Just remove unnecessary checks, no functional changes intended. Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Remove is_entry_func() and kernel_entry_endTiezhu Yang
For now, the related code of is_entry_func() is useless, so they can be removed. Then the symbol kernel_entry_end is not used any more, so it can be removed too. Link: https://lore.kernel.org/lkml/kjiyla6qj3l7ezspitulrdoc5laj2e6hoecvd254hssnpddczm@g6nkaombh6va/ Suggested-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn>
2025-12-31LoongArch: Use UNWIND_HINT_END_OF_STACK for entry pointsTiezhu Yang
kernel_entry() and smpboot_entry() are the last frames for ORC unwinder, so it is proper to use the annotation UNWIND_HINT_END_OF_STACK for them. Link: https://lore.kernel.org/lkml/ots6w2ntyudj5ucs5eowncta2vmfssatpcqwzpar3ekk577hxi@j45dd4dmwx6x/ Suggested-by: Josh Poimboeuf <jpoimboe@kernel.org> Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Set correct protection_map[] for VM_NONE/VM_SHAREDHuacai Chen
For 32BIT platform _PAGE_PROTNONE is 0, so set a VMA to be VM_NONE or VM_SHARED will make pages non-present, then cause Oops with kernel page fault. Fix it by set correct protection_map[] for VM_NONE/VM_SHARED, replacing _PAGE_PROTNONE with _PAGE_PRESENT. Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-31LoongArch: Complete CPUCFG registers definitionHuacai Chen
According to the "LoongArch Reference Manual Volume 1: Basic Architecture", begin with LA664 CPU core there are more features supported which are indicated in CPUCFG2 and CPUCFG3. This patch completes the definitions of them so as to match the architecture specification. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
2025-12-30riscv: fix KUnit test_kprobes crash when building with ClangJiakai Xu
Clang misinterprets the placement of test_kprobes_addresses and test_kprobes_functions arrays when they are not explicitly assigned to a data section. This can lead to kmalloc_array() allocation errors and KUnit failures. When testing the Clang-compiled code in QEMU, this warning was emitted: WARNING: CPU: 1 PID: 3000 at mm/page_alloc.c:5159 __alloc_frozen_pages_noprof+0xe6/0x2fc mm/page_alloc.c:5159 Further investigation revealed that the test_kprobes_addresses array appeared to have over 100,000 elements, including invalid addresses; whereas, according to test-kprobes-asm.S, test_kprobes_addresses should only have 25 elements. When compiling the kernel with GCC, the kernel boots correctly. This patch fixes the issue by adding .section .rodata to explicitly place arrays in the read-only data segment. For detailed debug and analysis, see: https://github.com/j1akai/temp/blob/main/20251113/readme.md v1 -> v2： - Drop changes to .align, and .globl. Signed-off-by: Jiakai Xu <xujiakai2025@iscas.ac.cn> Signed-off-by: Jiakai Xu <jiakaiPeanut@gmail.com> Link: https://patch.msgid.link/738dd4e2.ff73.19a7cd7b4d5.Coremail.xujiakai2025@iscas.ac.cn Link: https://github.com/llvm/llvm-project/issues/168308 Link: https://patch.msgid.link/20251226032317.1523764-1-jiakaiPeanut@gmail.com Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-31arm64: dts: freescale: Add FRDM-IMX91 basic supportJoseph Guo
The FRDM i.MX 91 development board is a low-cost and compact developmentboard featuring the i.MX 91 applications processor: https://www.nxp.com/design/design-center/development-boards-and-designs/FRDM-IMX91 Add FRDM-IMX91 board dts support. - Enable ADC1. - Enable lpuart1 and lpuart5. - Enable network eqos and fec. - Enable I2C bus and children nodes under I2C bus. - Enable USB and related nodes. - Enable uSDHC1, uSDHC2 and uSDHC3. - Enable MU1 and MU2. - Enable Watchdog3. - Enable MQS Co-developed-by: Tom Zheng <haidong.zheng@nxp.com> Signed-off-by: Tom Zheng <haidong.zheng@nxp.com> Co-developed-by: Steven Yang <steven.yang@nxp.com> Signed-off-by: Steven Yang <steven.yang@nxp.com> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Reviewed-by: Francesco Valla <francesco@valla.it> Tested-by: Francesco Valla <francesco@valla.it> Signed-off-by: Joseph Guo <qijian.guo@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30riscv: Sanitize syscall table indexing under speculationLukas Gerlach
The syscall number is a user-controlled value used to index into the syscall table. Use array_index_nospec() to clamp this value after the bounds check to prevent speculative out-of-bounds access and subsequent data leakage via cache side channels. Signed-off-by: Lukas Gerlach <lukas.gerlach@cispa.de> Link: https://patch.msgid.link/20251218191332.35849-3-lukas.gerlach@cispa.de Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-30riscv: boot: Always make Image from vmlinux, not vmlinux.unstrippedVivian Wang
Since commit 4b47a3aefb29 ("kbuild: Restore pattern to avoid stripping .rela.dyn from vmlinux") vmlinux has .rel*.dyn preserved. Therefore, use vmlinux to produce Image, not vmlinux.unstripped. Doing so fixes booting a RELOCATABLE=y Image with kexec. The problem is caused by this chain of events: - Since commit 3e86e4d74c04 ("kbuild: keep .modinfo section in vmlinux.unstripped"), vmlinux.unstripped gets a .modinfo section. - The .modinfo section has SHF_ALLOC, so it ends up in Image, at the end of it. - The Image header's image_size field does not expect to include .modinfo and does not account for it, since it should not be in Image. - If .modinfo is large enough, the file size of Image ends up larger than image_size, which eventually leads to it failing sanity_check_segment_list(). Using vmlinux instead of vmlinux.unstripped means that the unexpected .modinfo section is gone from Image, fixing the file size problem. Cc: stable@vger.kernel.org Fixes: 3e86e4d74c04 ("kbuild: keep .modinfo section in vmlinux.unstripped") Signed-off-by: Vivian Wang <wangruikang@iscas.ac.cn> Reviewed-by: Nathan Chancellor <nathan@kernel.org> Tested-by: Han Gao <gaohan@iscas.ac.cn> Link: https://patch.msgid.link/20251230-riscv-vmlinux-not-unstripped-v1-1-15f49df880df@iscas.ac.cn Signed-off-by: Paul Walmsley <pjw@kernel.org>
2025-12-31arm64: dts: imx8mp: Update Data Modul i.MX8M Plus eDM SBC DT to rev.903Marek Vasut
Update the DT to match newest Data Modul i.MX8M Plus eDM SBC rev.903 board which implements significant changes. Keep some of the rev.900 and rev.902 nodes in the DT so that a DTO can be used to support old rev.900 and rev.902 boards easily. The changes from rev.900 to rev.902 are: - Both ethernet PHYs replaced from AR8031 to BCM54213PE - Both ethernet PHYs MDIO address changed - PCIe WiFi now comes with dedicated regulator - I2C TPM chip address - Additional GPIO expander for LVDS panel control added - Current EEPROM I2C address changed - Another optional EEPROM added onto another I2C bus The changes from rev.902 to rev.903 are: - Additional GPIO expander for WiFi and LVDS panel control added - Multiple GPIOs are reassigned Signed-off-by: Marek Vasut <marek.vasut@mailbox.org> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-31arm64: dts: imx8mp-evk: add camera ov5640 and related nodesFrank Li
Add camera ov5640 and related nodes. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-31arm64: dts: colibri-imx8x: Add cma memoryPhilippe Schenker
Add CMA in device tree and set its size to 416MiB for all Colibri iMX8X. The size is tuned to be enough to play full HD video using gst-play and to fit in the SKU with the lowest amount of RAM (1GB). Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-31arm64: dts: colibri-imx8x: Add wi-fi 32kHz clockMax Krummenacher
The Wi-Fi module requires a 32kHz clock to support Wi-Fi/BT low power operation. Setting the pinmuxing option on the connected pin to 32kHz is all needed to generated the signal. Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-31arm64: dts: colibri-imx8x: Add backlightPhilippe Schenker
Add a backlight node to colibri-imx8x. The node can be enabled from an overlay once display output is implemented. Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30ARM: dts: microchip: lan966x: Fix the access to the PHYs for pcb8290Horatiu Vultur
The problem is that the MDIO controller can't detect any of the PHYs. The reason is that the lan966x is not pulling high the GPIO 53 that is connected to the PHYs reset GPIO. Without doing this the PHYs are kept in reset. The mdio controller framework has the possibility to control a GPIO to release the reset of the PHYs. So take advantage of this and set line to be high before accessing the PHYs. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Link: https://lore.kernel.org/r/20251119134750.394655-1-horatiu.vultur@microchip.com [claudiu.beznea: add microchip in patch title, s/possiblity/possibility in patch description] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
2025-12-30ARM: dts: imx: imx6sl: fix lcdif compatibleAndreas Kemnade
Fix lcdif compatible according to bindings doc. dtbs_check tested only, a glance at the datasheet shows that it should be the correct fallback compatible. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30ARM: imx_v6_v7_defconfig: enable EPD regulator needed for Kobo Clara 2eAndreas Kemnade
Kobo Clara 2e revision b requires the JD9930/FP9931 regulator driver for the EPD, so enable it. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30ARM: dts: imx: imx6sll-kobo-clara2e: add regulator for EPDAndreas Kemnade
Now there is a driver and binding for the JD9930, so add the information to the devicetree for revision b. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30ARM: dts: imx: imx6sll: fix lcdif compatibleAndreas Kemnade
Fix lcdif compatible according to bindings doc. dtbs_check tested only, a glance at the datasheet shows that it should be the correct fallback compatible. Signed-off-by: Andreas Kemnade <andreas@kemnade.info> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Add Apalis iMX8QPFrancesco Dolcini
Add support for the Apalis iMX8QP SoM mated with Apalis Ixora and Apalis Evaluation board. Apalis iMX8QP is a variant of the Apalis iMX8QM, using an NXP i.MX8QP SoC instead of the i.MX8QM. The two SoCs are pin to pin compatible, with the i.MX8QP being a lower end variant, with a slower GPU and one Cortex A72 core instead of two. The two Apalis SoMs variants share the same schematics and PCB, and the iMX8QP variant exists only on revision V1.1 of board. Link: https://www.nxp.com/products/i.MX8 Link: https://www.toradex.com/computer-on-modules/apalis-arm-family/nxp-imx-8 Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Add NXP i.MX8QP SoC dtsiFrancesco Dolcini
Add support for NXP i.MX8QP SoC, this is pin to pin compatible variant of the i.MX8QM, with a slower GPU and one Cortex A72 core instead of two. Link: https://www.nxp.com/products/i.MX8 Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx8qm: Add CPU cluster labelsFrancesco Dolcini
Add labels to the cpu cluster nodes to prepare for the addition of the i.MX8QP SoC in which these nodes would need to be adjusted from another DT file. Signed-off-by: Francesco Dolcini <francesco.dolcini@toradex.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Use lowercase hexKrzysztof Kozlowski
The DTS code coding style expects lowercase hex for values and unit addresses. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Minor whitespace cleanupKrzysztof Kozlowski
The DTS code coding style expects exactly one space around '=' and before '{' characters. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Use hyphen in node namesKrzysztof Kozlowski
DTS coding style prefers hyphens instead of underscores in the node names. Change should be safe, because node names are not considered an ABI. Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx94: add mt35xu512aba spi nor supportHaibo Chen
Add mt35xu512aba spi nor support on imx943-evk board. This nor chip support OCT DTR mode. For the reset pin, since the nor chip side need 1.8v IO voltage for reset pin, but the IO expander side use 3.3v IO voltage, so to make circuit safe, need to config the pad as OPEN DRAIN. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: imx94: add xspi device nodeHaibo Chen
imx94 has two xspi, add these device nodes. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Add i.MX952 EVK basic device treePeng Fan
Add i.MX952 EVK basic device tree, with UART1, SDHC[1,2] supported. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2025-12-30arm64: dts: freescale: Add initial device tree for i.MX952Peng Fan
i.MX952 is designed for AI-powered sensor fusion and vision sensing applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and NXP eIQ NPU and advanced graphics, video and advanced security with edgelock. Product info could be found at: https://www.nxp.com/products/i.MX-952 The basic device tree includes: - clock, pin, power header files - device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter, eDMA, MU, SPI, UART, I2C, USB and etc Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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