linux-stable.git/tools/testing/selftests/kvm, branch v5.6

selftests: KVM: Remove unused x86_register enum

2020-02-12T19:09:45+00:00

x86_register enum is not used, let's remove it.

Signed-off-by: Eric Auger 
Suggested-by: Vitaly Kuznetsov 
Signed-off-by: Paolo Bonzini

selftests: KVM: SVM: Add vmcall test

2020-02-12T19:09:39+00:00

L2 guest calls vmcall and L1 checks the exit status does
correspond.

Signed-off-by: Eric Auger 
Reviewed-by: Vitaly Kuznetsov 
Reviewed-by: Miaohe Lin 
Tested-by: Wei Huang 
Signed-off-by: Paolo Bonzini

selftests: KVM: AMD Nested test infrastructure

2020-02-12T19:09:39+00:00

Add the basic infrastructure needed to test AMD nested SVM.
This is largely copied from the KVM unit test infrastructure.

Signed-off-by: Eric Auger 
Reviewed-by: Vitaly Kuznetsov 
Signed-off-by: Paolo Bonzini

selftests: KVM: Replace get_{gdt,idt}_base() by get_{gdt,idt}()

2020-02-12T19:09:38+00:00

get_gdt_base() and get_idt_base() only return the base address
of the descriptor tables. Soon we will need to get the size as well.
Change the prototype of those functions so that they return
the whole desc_ptr struct instead of the address field.

Signed-off-by: Eric Auger 
Reviewed-by: Vitaly Kuznetsov 
Reviewed-by: Miaohe Lin 
Reviewed-by: Wei Huang 
Reviewed-by: Krish Sadhukhan 
Signed-off-by: Paolo Bonzini

Merge tag 'kvm-s390-next-5.6-1' of git://git.kernel.org/pub/scm/linux/kernel/git/kvms390/linux into HEAD

2020-02-05T15:15:05+00:00

KVM: s390: Fixes and cleanups for 5.6
- fix register corruption
- ENOTSUPP/EOPNOTSUPP mixed
- reset cleanups/fixes
- selftests

Merge tag 'kvm-5.6-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm

2020-01-31T17:30:41+00:00

Pull KVM updates from Paolo Bonzini:
 "This is the first batch of KVM changes.

  ARM:
   - cleanups and corner case fixes.

  PPC:
   - Bugfixes

  x86:
   - Support for mapping DAX areas with large nested page table entries.

   - Cleanups and bugfixes here too. A particularly important one is a
     fix for FPU load when the thread has TIF_NEED_FPU_LOAD. There is
     also a race condition which could be used in guest userspace to
     exploit the guest kernel, for which the embargo expired today.

   - Fast path for IPI delivery vmexits, shaving about 200 clock cycles
     from IPI latency.

   - Protect against "Spectre-v1/L1TF" (bring data in the cache via
     speculative out of bound accesses, use L1TF on the sibling
     hyperthread to read it), which unfortunately is an even bigger
     whack-a-mole game than SpectreV1.

  Sean continues his mission to rewrite KVM. In addition to a sizable
  number of x86 patches, this time he contributed a pretty large
  refactoring of vCPU creation that affects all architectures but should
  not have any visible effect.

  s390 will come next week together with some more x86 patches"

* tag 'kvm-5.6-1' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (204 commits)
  x86/KVM: Clean up host's steal time structure
  x86/KVM: Make sure KVM_VCPU_FLUSH_TLB flag is not missed
  x86/kvm: Cache gfn to pfn translation
  x86/kvm: Introduce kvm_(un)map_gfn()
  x86/kvm: Be careful not to clear KVM_VCPU_FLUSH_TLB bit
  KVM: PPC: Book3S PR: Fix -Werror=return-type build failure
  KVM: PPC: Book3S HV: Release lock on page-out failure path
  KVM: arm64: Treat emulated TVAL TimerValue as a signed 32-bit integer
  KVM: arm64: pmu: Only handle supported event counters
  KVM: arm64: pmu: Fix chained SW_INCR counters
  KVM: arm64: pmu: Don't mark a counter as chained if the odd one is disabled
  KVM: arm64: pmu: Don't increment SW_INCR if PMCR.E is unset
  KVM: x86: Use a typedef for fastop functions
  KVM: X86: Add 'else' to unify fastop and execute call path
  KVM: x86: inline memslot_valid_for_gpte
  KVM: x86/mmu: Use huge pages for DAX-backed files
  KVM: x86/mmu: Remove lpage_is_disallowed() check from set_spte()
  KVM: x86/mmu: Fold max_mapping_level() into kvm_mmu_hugepage_adjust()
  KVM: x86/mmu: Zap any compound page when collapsing sptes
  KVM: x86/mmu: Remove obsolete gfn restoration in FNAME(fetch)
  ...

selftests: KVM: testing the local IRQs resets

2020-01-31T12:17:21+00:00

Local IRQs are reset by a normal cpu reset.  The initial cpu reset and
the clear cpu reset, as superset of the normal reset, both clear the
IRQs too.

Let's inject an interrupt to a vCPU before calling a reset and see if
it is gone after the reset.

We choose to inject only an emergency interrupt at this point and can
extend the test to other types of IRQs later.

Signed-off-by: Pierre Morel 
Signed-off-by: Janosch Frank 
[minor fixups]
Reviewed-by: Cornelia Huck 
Reviewed-by: Thomas Huth 
Link: https://lore.kernel.org/r/20200131100205.74720-7-frankja@linux.ibm.com
Signed-off-by: Christian Borntraeger

selftests: KVM: s390x: Add reset tests

2020-01-31T12:17:21+00:00

Test if the registers end up having the correct values after a normal,
initial and clear reset.

Signed-off-by: Janosch Frank 
Reviewed-by: Thomas Huth 
Reviewed-by: Cornelia Huck 
Link: https://lore.kernel.org/r/20200131100205.74720-6-frankja@linux.ibm.com
Signed-off-by: Christian Borntraeger

selftests: KVM: Add fpu and one reg set/get library functions

2020-01-31T12:17:21+00:00

Add library access to more registers.

Signed-off-by: Janosch Frank 
Reviewed-by: Thomas Huth 
Reviewed-by: Cornelia Huck 
Link: https://lore.kernel.org/r/20200131100205.74720-5-frankja@linux.ibm.com
Signed-off-by: Christian Borntraeger

tools/x86: Sync msr-index.h from kernel sources

2020-01-13T16:42:57+00:00

Sync msr-index.h to pull in recent renames of the IA32_FEATURE_CONTROL
MSR definitions.  Update KVM's VMX selftest and turbostat accordingly.
Keep the full name in turbostat's output to avoid breaking someone's
workflow, e.g. if a script is looking for the full name.

While using the renamed defines is by no means necessary, do the sync
now to avoid leaving a landmine that will get stepped on the next time
msr-index.h needs to be refreshed for some other reason.

No functional change intended.

Signed-off-by: Sean Christopherson 
Signed-off-by: Borislav Petkov 
Link: https://lkml.kernel.org/r/20191221044513.21680-4-sean.j.christopherson@intel.com