<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/tools/perf, branch master</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>Merge tag 'perf-tools-for-v7.3-2026-08-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools</title>
<updated>2026-08-22T15:47:50+00:00</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2026-08-22T15:47:50+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=473f6c8f437b049f8ec015d57cd59bb983b1d85c'/>
<id>473f6c8f437b049f8ec015d57cd59bb983b1d85c</id>
<content type='text'>
Pull perf tools updates from Namhyung Kim:
 "perf c2c:

   - Add 'function view' in perf c2c report TUI (switched by pressing
     'TAB' in the cacheline view) to organize samples around functions
     rather than cachelines in 3-level hierarchy:

	Level 1: Read-side function (sorted by estimated Cycles %)
	Level 2:   Contending writer functions (sorted by Store count)
	Level 3:     Shared cacheline addresses

     Users can navigate the entries and fold/unfold using 'e' key. An
     example output would look like below:

	Shared Data Functions Table     (19 entries, sorted on Cycles %)
	   Cycles    Store
	        %    count  Function / Contending function / Cacheline
	----------------------------------------------------------------------
	+  35.67%      876  + [k] cpupri_set
	+  24.31%      424  + [k] pull_rt_task
	-  16.53%      555  - [k] dequeue_pushable_task
	               145    - [k] pull_rt_task
	               145        0xff2d0082809da080
	               139    - [k] enqueue_pushable_task
	                70        0xff2d00a2071f9640
	                69        0xff2d0082809da000

  python module support:

   - Extend "perf" python module so that it can be fully functional. The
     goal is to run scripts directly, not by 'perf script' command. This
     would give better performance as well as more control to build
     standalone programs with UI.

   - Add LiveSession helper (perf_live.py) to enable live event
     collection directly from Python using perf.evlist and
     perf.parse_events.

  perf stat:

   - Add --hide-zero-events option to suppress zero-count events
   - Reject conflicting --field-separator and --json-output options
   - Fix duplicate event output with --for-each-cgroup

  perf sched latency:

   - Add -H/--histogram and --hist-mode (log|linear) options to show
     scheduler wait latency histograms
   - Add --time option to filter analysis by time span in 'perf sched
     latency'

  ARM CoreSight:

   - Synthesize callchains for instruction samples from CoreSight trace
     using thread stack ('--itrace=g...')
   - Support call indentation ('perf script -F +callindent') to display
     call depth hierarchy on branch samples
   - Decode ETE (Embedded Trace Extension) exception packets

  Build system:

   - Add 'make install-build-deps' target to install required packages
   - Parallelize JSON and metric pre-computation in jevents.py for
     faster builds

  Vendor event/metric updates:

   - Add Intel Nova Lake events and update tables for existing models
   - Update AMD Zen 5 and Zen 6 core events
   - Update Arm64 Tegra410 metrics and PowerPC hcalls

  Internal changes and fixes:

   - Harden trace-event and synthetic event parsing against corrupted
     data
   - Fix unwinding of multi-threaded processes in libdw unwinder
   - Fix memory leaks in various commands and python bindings
   - Speed up 'perf test' shell tests"

* tag 'perf-tools-for-v7.3-2026-08-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (232 commits)
  perf vendor events arm64: Fix Tegra410 Olympus event 0x0197
  perf vendor events arm64: fix swapped MetricGroup for Tegra410 L1 prefetcher metrics
  perf evlist: Warn when 'sleep' workload is used without system-wide (-a) option
  perf c2c: document function view in perf-c2c man page
  perf c2c: add function view browser UI and cacheline detail
  perf c2c: build and finalize the function view hierarchy
  perf c2c: add function view hierarchy entry creation
  perf c2c: add function view stats merge and memory management
  perf c2c: add HPP list parsing for function view columns
  perf c2c: add column rendering for function view
  perf c2c: add function view model skeleton
  perf c2c: extract shared data structures into util/c2c.h
  perf test sample-parsing: Validate PERF_FORMAT_GROUP values without LOST
  perf dso: Replace assert with runtime check in dso__read_symbol()
  perf dso: Guard against cache underflow on short reads in dso_cache__memcpy()
  perf dso: Use stored fd error instead of stale errno in file_read() and file_size()
  perf dso: Guard close() against invalid fd in dso__decompress_kmodule_path()
  perf dso: Guard against errno==0 when dso__get_filename() returns NULL
  perf build: install-build-deps: add RHEL family devel package mapping
  perf build: Remove leftover feature tests for removed cxx and clang support
  ...
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Pull perf tools updates from Namhyung Kim:
 "perf c2c:

   - Add 'function view' in perf c2c report TUI (switched by pressing
     'TAB' in the cacheline view) to organize samples around functions
     rather than cachelines in 3-level hierarchy:

	Level 1: Read-side function (sorted by estimated Cycles %)
	Level 2:   Contending writer functions (sorted by Store count)
	Level 3:     Shared cacheline addresses

     Users can navigate the entries and fold/unfold using 'e' key. An
     example output would look like below:

	Shared Data Functions Table     (19 entries, sorted on Cycles %)
	   Cycles    Store
	        %    count  Function / Contending function / Cacheline
	----------------------------------------------------------------------
	+  35.67%      876  + [k] cpupri_set
	+  24.31%      424  + [k] pull_rt_task
	-  16.53%      555  - [k] dequeue_pushable_task
	               145    - [k] pull_rt_task
	               145        0xff2d0082809da080
	               139    - [k] enqueue_pushable_task
	                70        0xff2d00a2071f9640
	                69        0xff2d0082809da000

  python module support:

   - Extend "perf" python module so that it can be fully functional. The
     goal is to run scripts directly, not by 'perf script' command. This
     would give better performance as well as more control to build
     standalone programs with UI.

   - Add LiveSession helper (perf_live.py) to enable live event
     collection directly from Python using perf.evlist and
     perf.parse_events.

  perf stat:

   - Add --hide-zero-events option to suppress zero-count events
   - Reject conflicting --field-separator and --json-output options
   - Fix duplicate event output with --for-each-cgroup

  perf sched latency:

   - Add -H/--histogram and --hist-mode (log|linear) options to show
     scheduler wait latency histograms
   - Add --time option to filter analysis by time span in 'perf sched
     latency'

  ARM CoreSight:

   - Synthesize callchains for instruction samples from CoreSight trace
     using thread stack ('--itrace=g...')
   - Support call indentation ('perf script -F +callindent') to display
     call depth hierarchy on branch samples
   - Decode ETE (Embedded Trace Extension) exception packets

  Build system:

   - Add 'make install-build-deps' target to install required packages
   - Parallelize JSON and metric pre-computation in jevents.py for
     faster builds

  Vendor event/metric updates:

   - Add Intel Nova Lake events and update tables for existing models
   - Update AMD Zen 5 and Zen 6 core events
   - Update Arm64 Tegra410 metrics and PowerPC hcalls

  Internal changes and fixes:

   - Harden trace-event and synthetic event parsing against corrupted
     data
   - Fix unwinding of multi-threaded processes in libdw unwinder
   - Fix memory leaks in various commands and python bindings
   - Speed up 'perf test' shell tests"

* tag 'perf-tools-for-v7.3-2026-08-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (232 commits)
  perf vendor events arm64: Fix Tegra410 Olympus event 0x0197
  perf vendor events arm64: fix swapped MetricGroup for Tegra410 L1 prefetcher metrics
  perf evlist: Warn when 'sleep' workload is used without system-wide (-a) option
  perf c2c: document function view in perf-c2c man page
  perf c2c: add function view browser UI and cacheline detail
  perf c2c: build and finalize the function view hierarchy
  perf c2c: add function view hierarchy entry creation
  perf c2c: add function view stats merge and memory management
  perf c2c: add HPP list parsing for function view columns
  perf c2c: add column rendering for function view
  perf c2c: add function view model skeleton
  perf c2c: extract shared data structures into util/c2c.h
  perf test sample-parsing: Validate PERF_FORMAT_GROUP values without LOST
  perf dso: Replace assert with runtime check in dso__read_symbol()
  perf dso: Guard against cache underflow on short reads in dso_cache__memcpy()
  perf dso: Use stored fd error instead of stale errno in file_read() and file_size()
  perf dso: Guard close() against invalid fd in dso__decompress_kmodule_path()
  perf dso: Guard against errno==0 when dso__get_filename() returns NULL
  perf build: install-build-deps: add RHEL family devel package mapping
  perf build: Remove leftover feature tests for removed cxx and clang support
  ...
</pre>
</div>
</content>
</entry>
<entry>
<title>perf vendor events arm64: Fix Tegra410 Olympus event 0x0197</title>
<updated>2026-08-18T21:31:18+00:00</updated>
<author>
<name>Besar Wicaksono</name>
<email>bwicaksono@nvidia.com</email>
</author>
<published>2026-08-13T17:01:55+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9453bc6a69ef43755f1c28d5688cacdd69fa16bd'/>
<id>9453bc6a69ef43755f1c28d5688cacdd69fa16bd</id>
<content type='text'>
The name and description for NVIDIA Tegra410 Olympus implementation-defined
event 0x0197 incorrectly indicate a TXREQ limit between one quarter and
one half. Correct them to describe a TXREQ limit below one half.

Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Besar Wicaksono &lt;bwicaksono@nvidia.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The name and description for NVIDIA Tegra410 Olympus implementation-defined
event 0x0197 incorrectly indicate a TXREQ limit between one quarter and
one half. Correct them to describe a TXREQ limit below one half.

Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Besar Wicaksono &lt;bwicaksono@nvidia.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf vendor events arm64: fix swapped MetricGroup for Tegra410 L1 prefetcher metrics</title>
<updated>2026-08-18T21:31:18+00:00</updated>
<author>
<name>Saurav Sachidanand</name>
<email>sauravsc@amazon.com</email>
</author>
<published>2026-08-13T17:01:54+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=2d85e13c5526eee5f4d5670472a949f1489707ed'/>
<id>2d85e13c5526eee5f4d5670472a949f1489707ed</id>
<content type='text'>
The L1D prefetcher metrics (l1d_cache_rw_miss_ratio, l1d_demand_accesses,
etc.) were incorrectly assigned to MetricGroup "L1I_Prefetcher_Effectiveness"
and vice versa. This causes 'perf stat --metric-group L1D_Prefetcher_Effectiveness'
to display L1I metrics, which is misleading.

Swap the MetricGroup assignments so L1D metrics are in the L1D group and
L1I metrics are in the L1I group.

Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Saurav Sachidanand &lt;sauravsc@amazon.com&gt;
Reviewed-by: Besar Wicaksono &lt;bwicaksono@nvidia.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
The L1D prefetcher metrics (l1d_cache_rw_miss_ratio, l1d_demand_accesses,
etc.) were incorrectly assigned to MetricGroup "L1I_Prefetcher_Effectiveness"
and vice versa. This causes 'perf stat --metric-group L1D_Prefetcher_Effectiveness'
to display L1I metrics, which is misleading.

Swap the MetricGroup assignments so L1D metrics are in the L1D group and
L1I metrics are in the L1I group.

Fixes: 86ff690f45cc ("perf vendor events arm64: Add Tegra410 Olympus PMU events")
Signed-off-by: Saurav Sachidanand &lt;sauravsc@amazon.com&gt;
Reviewed-by: Besar Wicaksono &lt;bwicaksono@nvidia.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf evlist: Warn when 'sleep' workload is used without system-wide (-a) option</title>
<updated>2026-08-17T23:04:06+00:00</updated>
<author>
<name>Ian Rogers</name>
<email>irogers@google.com</email>
</author>
<published>2026-08-06T04:14:14+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=78148c85297024ffe7a709acb7cc4fc907271176'/>
<id>78148c85297024ffe7a709acb7cc4fc907271176</id>
<content type='text'>
A common mistake when trying to record system-wide profiles for a given
duration is running commands like 'perf record sleep 1' or 'perf stat
sleep 1' without passing '-a' / '--all-cpus'. When '-a' is omitted, perf
defaults to per-process monitoring of the sleep process itself, which
does not collect system-wide activity and records very few events.

Add a warning in evlist__prepare_workload() when the workload executable
is 'sleep' and system-wide mode is not enabled.

Assisted-by: Antigravity:gemini-3.6-flash
Signed-off-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
A common mistake when trying to record system-wide profiles for a given
duration is running commands like 'perf record sleep 1' or 'perf stat
sleep 1' without passing '-a' / '--all-cpus'. When '-a' is omitted, perf
defaults to per-process monitoring of the sleep process itself, which
does not collect system-wide activity and records very few events.

Add a warning in evlist__prepare_workload() when the workload executable
is 'sleep' and system-wide mode is not enabled.

Assisted-by: Antigravity:gemini-3.6-flash
Signed-off-by: Ian Rogers &lt;irogers@google.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: document function view in perf-c2c man page</title>
<updated>2026-08-17T23:04:06+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:23+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=16e113d46d29eb8bf13a5a58de6fb38f24f1aec2'/>
<id>16e113d46d29eb8bf13a5a58de6fb38f24f1aec2</id>
<content type='text'>
Describe the function view hierarchy (read-side function -&gt; contending
writer function -&gt; shared cachelines), the per-level indentation, and the
keys, with a worked example.

Document that reliable function attribution requires `iaddr` in
`--coalesce`, that the reader and writer may be the same function, and why
the coalesced function view cannot distinguish same-thread from
different-thread accesses in that case. Also document that verbose mode
includes code addresses in function rows.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Describe the function view hierarchy (read-side function -&gt; contending
writer function -&gt; shared cachelines), the per-level indentation, and the
keys, with a worked example.

Document that reliable function attribution requires `iaddr` in
`--coalesce`, that the reader and writer may be the same function, and why
the coalesced function view cannot distinguish same-thread from
different-thread accesses in that case. Also document that verbose mode
includes code addresses in function rows.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: add function view browser UI and cacheline detail</title>
<updated>2026-08-17T23:04:05+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:22+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=1975d27d11924d99319562889d8a15214bb84cc7'/>
<id>1975d27d11924d99319562889d8a15214bb84cc7</id>
<content type='text'>
Add the browser front end: create/run/delete the hist_browser and add the
title. The d shortcut opens the existing per-cacheline detail view for the
selected level-3 cacheline. Level-3 entries retain the source cacheline
index, so the shortcut can locate the original entry without relying on a
potentially ambiguous virtual address.

Report a warning when the common model rejects a cacheline coalescing field
list without `iaddr`. Without it, the detail histograms may already have
merged samples from different functions and cannot support reliable
function attribution.

Keep visible-row accounting local to the function view by wrapping the
generic browser refresh callback and recounting the currently reachable
hierarchy before each redraw. This keeps navigation correct when a level-1
row is collapsed while level-3 descendants remain expanded, without adding
C2C-specific hooks to the shared hist_browser. Also handle Ctrl-C like the
other function-view exit keys.

Keep callchains hidden while the function browser runs, restoring the
user's setting while opening the cacheline detail view.

Wire the builder into perf_c2c__browse_function_view().

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the browser front end: create/run/delete the hist_browser and add the
title. The d shortcut opens the existing per-cacheline detail view for the
selected level-3 cacheline. Level-3 entries retain the source cacheline
index, so the shortcut can locate the original entry without relying on a
potentially ambiguous virtual address.

Report a warning when the common model rejects a cacheline coalescing field
list without `iaddr`. Without it, the detail histograms may already have
merged samples from different functions and cannot support reliable
function attribution.

Keep visible-row accounting local to the function view by wrapping the
generic browser refresh callback and recounting the currently reachable
hierarchy before each redraw. This keeps navigation correct when a level-1
row is collapsed while level-3 descendants remain expanded, without adding
C2C-specific hooks to the shared hist_browser. Also handle Ctrl-C like the
other function-view exit keys.

Keep callchains hidden while the function browser runs, restoring the
user's setting while opening the cacheline detail view.

Wire the builder into perf_c2c__browse_function_view().

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: build and finalize the function view hierarchy</title>
<updated>2026-08-17T23:04:05+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:21+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=776356199431d92469276fc9b4b9229f803929c4'/>
<id>776356199431d92469276fc9b4b9229f803929c4</id>
<content type='text'>
Add the builder that walks the top-level cacheline entries and, for each
read-side function, correlates the functions that write the same lines
(level 2) and the specific cachelines they contend over (level 3) within
each retained detail histogram. Aggregate the write traffic per contending
function, resort by store count, and prune writers/functions with no
contention. The finalize pass then computes the Cycles % denominator from
the surviving level-1 entries after pruning, so the column shows each
function's share of the functions retained in the table rather than of the
whole recording -- the semantics documented for Cycles % in perf-c2c.txt.

Expose c2c_function__build() and c2c_function__reset() for the TUI front
end added by the next patch. The builder requires iaddr in the cacheline
coalescing fields and returns the completed hists through an output
argument. Validate the inputs before replacing an existing model.

Function-view entries do not carry callchains. Suppress callchain handling
while building and tearing down the model so the common API does not depend
on the caller's current callchain setting.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the builder that walks the top-level cacheline entries and, for each
read-side function, correlates the functions that write the same lines
(level 2) and the specific cachelines they contend over (level 3) within
each retained detail histogram. Aggregate the write traffic per contending
function, resort by store count, and prune writers/functions with no
contention. The finalize pass then computes the Cycles % denominator from
the surviving level-1 entries after pruning, so the column shows each
function's share of the functions retained in the table rather than of the
whole recording -- the semantics documented for Cycles % in perf-c2c.txt.

Expose c2c_function__build() and c2c_function__reset() for the TUI front
end added by the next patch. The builder requires iaddr in the cacheline
coalescing fields and returns the completed hists through an output
argument. Validate the inputs before replacing an existing model.

Function-view entries do not carry callchains. Suppress callchain handling
while building and tearing down the model so the common API does not depend
on the caller's current callchain setting.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: add function view hierarchy entry creation</title>
<updated>2026-08-17T23:04:05+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:20+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=473a047faa8f12cc529e31cdadaf8942fd6765a2'/>
<id>473a047faa8f12cc529e31cdadaf8942fd6765a2</id>
<content type='text'>
Add the entry-creation layer: owned-reference child allocation and
insertion, and the level-1/2/3 lookup-or-create functions keyed by
function symbol (level 1 read-side, level 2 writer) and by the source
cacheline's existing index (level 3).

Give synthetic children normal entry operations and acquire their thread
and map-symbol references. This lets the hierarchy teardown use
hist_entry__delete() for the common fields while the function-view free
callback handles the private child tree and containing allocation.

Reuse cacheline_idx to preserve the source entry identity without adding
function-view-only state. Add c2c_function__find_cacheline() to locate the
original cacheline entry by the same index.

These are driven by the hierarchy builder in the next patch and are
__maybe_unused until then.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the entry-creation layer: owned-reference child allocation and
insertion, and the level-1/2/3 lookup-or-create functions keyed by
function symbol (level 1 read-side, level 2 writer) and by the source
cacheline's existing index (level 3).

Give synthetic children normal entry operations and acquire their thread
and map-symbol references. This lets the hierarchy teardown use
hist_entry__delete() for the common fields while the function-view free
callback handles the private child tree and containing allocation.

Reuse cacheline_idx to preserve the source entry identity without adding
function-view-only state. Add c2c_function__find_cacheline() to locate the
original cacheline entry by the same index.

These are driven by the hierarchy builder in the next patch and are
__maybe_unused until then.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: add function view stats merge and memory management</title>
<updated>2026-08-17T23:04:05+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:19+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=929c4ebb542ff3015385e9ba11294ff0cc68b7b6'/>
<id>929c4ebb542ff3015385e9ba11294ff0cc68b7b6</id>
<content type='text'>
Add the per-entry stats/cstats aggregation helpers and hierarchy teardown.
Child common fields are released through hist_entry__delete(), while the
function-view free callback handles the private child tree and containing
allocation. Also add a helper for pruning writer entries with no stores or
cacheline children.

These are used by the entry-creation and builder patches that follow and
are __maybe_unused until then.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the per-entry stats/cstats aggregation helpers and hierarchy teardown.
Child common fields are released through hist_entry__delete(), while the
function-view free callback handles the private child tree and containing
allocation. Also add a helper for pruning writer entries with no stores or
cacheline children.

These are used by the entry-creation and builder patches that follow and
are __maybe_unused until then.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>perf c2c: add HPP list parsing for function view columns</title>
<updated>2026-08-17T23:04:05+00:00</updated>
<author>
<name>Jiebin Sun</name>
<email>jiebin.sun@intel.com</email>
</author>
<published>2026-08-17T09:46:18+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=e888662432362ccf589c7b6919464cbc22064552'/>
<id>e888662432362ccf589c7b6919464cbc22064552</id>
<content type='text'>
Add the parser that builds the function view's local HPP output and
sort lists from field strings. This includes dimension lookup, comparator
wrappers, c2c_fmt allocation, and the initialization entry points used by
the hierarchy builder.

The generic perf_hpp__setup_output_field() registers formats on the global
perf_hpp_list. Using it here would leave the function view's local list
without output columns and modify the cacheline view's list instead. Add
c2c_function_hists__setup_output_field() to append sort keys to the local
output list.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Add the parser that builds the function view's local HPP output and
sort lists from field strings. This includes dimension lookup, comparator
wrappers, c2c_fmt allocation, and the initialization entry points used by
the hierarchy builder.

The generic perf_hpp__setup_output_field() registers formats on the global
perf_hpp_list. Using it here would leave the function view's local list
without output columns and modify the cacheline view's list instead. Add
c2c_function_hists__setup_output_field() to append sort keys to the local
output list.

Signed-off-by: Jiebin Sun &lt;jiebin.sun@intel.com&gt;
Reviewed-by: Tianyou Li &lt;tianyou.li@intel.com&gt;
Reviewed-by: Wangyang Guo &lt;wangyang.guo@intel.com&gt;
Reviewed-by: Ian Rogers &lt;irogers@google.com&gt;
Cc: Dapeng Mi &lt;dapeng1.mi@linux.intel.com&gt;
Cc: James Clark &lt;james.clark@linaro.org&gt;
Cc: Thomas Falcon &lt;thomas.falcon@intel.com&gt;
Signed-off-by: Namhyung Kim &lt;namhyung@kernel.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
