<feed xmlns='http://www.w3.org/2005/Atom'>
<title>linux-stable.git/include/linux/spi/spi.h, branch linux-3.12.y</title>
<subtitle>Linux kernel stable tree</subtitle>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/'/>
<entry>
<title>Merge remote-tracking branch 'spi/topic/qspi' into spi-next</title>
<updated>2013-09-01T12:49:06+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-09-01T12:49:06+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=85cac431329bd09f7d30d489591d7af0d658b008'/>
<id>85cac431329bd09f7d30d489591d7af0d658b008</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'spi/topic/msglen' into spi-next</title>
<updated>2013-09-01T12:48:58+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-09-01T12:48:58+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=9020b75467ff81b2ae257bbf19acff462854d4ab'/>
<id>9020b75467ff81b2ae257bbf19acff462854d4ab</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'spi/topic/checks' into spi-next</title>
<updated>2013-09-01T12:48:48+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-09-01T12:48:48+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=db04e17055c2d912a847f02a10deee1d82f96300'/>
<id>db04e17055c2d912a847f02a10deee1d82f96300</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Merge remote-tracking branch 'spi/topic/quad' into spi-qspi</title>
<updated>2013-08-23T11:00:15+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-08-23T11:00:15+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=21e34a3306e7f0399cc0e10c24cb0e7790dfbcac'/>
<id>21e34a3306e7f0399cc0e10c24cb0e7790dfbcac</id>
<content type='text'>
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: DUAL and QUAD support</title>
<updated>2013-08-22T12:47:29+00:00</updated>
<author>
<name>wangyuhang</name>
<email>wangyuhang2014@gmail.com</email>
</author>
<published>2013-08-11T10:15:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=f477b7fb13df2b843997559ff34e87d054ba6538'/>
<id>f477b7fb13df2b843997559ff34e87d054ba6538</id>
<content type='text'>
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = &lt;1/2/4&gt;" in place of using
   "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
   previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
   SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
   (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
      single, dual and quad.
   (2)keep tx_nbits and rx_nbits are contained by @spi_device-&gt;mode
      example: if @spi_device-&gt;mode = DUAL, then tx/rx_nbits can not be set
               to QUAD(SPI_NBITS_QUAD)
   (3)if "@spi_device-&gt;mode &amp; SPI_3WIRE", then tx/rx_nbits should be in
      single(SPI_NBITS_SINGLE)

Signed-off-by: wangyuhang &lt;wangyuhang2014@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
fix the previous patch some mistake below:
1. DT in slave node, use "spi-tx-nbits = &lt;1/2/4&gt;" in place of using
   "spi-tx-dual, spi-tx-quad" directly, same to rx. So correct the
   previous way to get the property in @of_register_spi_devices().
2. Change the value of transfer bit macro(SPI_NBITS_SINGLE, SPI_NBITS_DUAL
   SPI_NBITS_QUAD) to 0x01, 0x02 and 0x04 to match the actual wires.
3. Add the following check
   (1)keep the tx_nbits and rx_nbits in spi_transfer is not beyond the
      single, dual and quad.
   (2)keep tx_nbits and rx_nbits are contained by @spi_device-&gt;mode
      example: if @spi_device-&gt;mode = DUAL, then tx/rx_nbits can not be set
               to QUAD(SPI_NBITS_QUAD)
   (3)if "@spi_device-&gt;mode &amp; SPI_3WIRE", then tx/rx_nbits should be in
      single(SPI_NBITS_SINGLE)

Signed-off-by: wangyuhang &lt;wangyuhang2014@gmail.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fix SPI_BIT_MASK so it always fits into 32-bits</title>
<updated>2013-08-02T10:31:22+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-08-01T22:08:57+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=b6aa23ccaea1548cfb404b41129717f13443bccf'/>
<id>b6aa23ccaea1548cfb404b41129717f13443bccf</id>
<content type='text'>
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:

drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]

Reported-by: kbuild test robot &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
On a 64-bit platform, ~0UL fills 64-bits, which causes SPI_BIT_MASK(32)
not to fit into 32 bits. This causes a warning when the result is assigned
to a 32-bit variable. Use ~0U instead to prevent this. This fixes:

drivers/spi/spi-gpio.c: In function 'spi_gpio_probe':
drivers/spi/spi-gpio.c:446:2: warning: large integer implicitly truncated to unsigned type [-Woverflow]

Reported-by: kbuild test robot &lt;fengguang.wu@intel.com&gt;
Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Provide core support for runtime PM during transfers</title>
<updated>2013-07-29T16:59:20+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-07-28T13:47:02+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=49834de234f3cf592c3d242c889ca603db8e7050'/>
<id>49834de234f3cf592c3d242c889ca603db8e7050</id>
<content type='text'>
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.

Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Most SPI drivers that implement runtime PM support use identical code to
do so: they acquire a runtime PM lock in prepare_transfer_hardware() and
then they release it in unprepare_transfer_hardware(). The variations in
this are mostly missing error checking and the choice to use autosuspend.

Since these runtime PM calls are normally the only thing in the prepare
and unprepare callbacks and the autosuspend API transparently does the
right thing on devices with autosuspend disabled factor all of this out
into the core with a flag to enable the behaviour.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
Reviewed-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Acked-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>driver: spi: Modify core to compute the message length</title>
<updated>2013-07-18T15:22:01+00:00</updated>
<author>
<name>Sourav Poddar</name>
<email>sourav.poddar@ti.com</email>
</author>
<published>2013-07-18T10:01:25+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=078726ce6d56a767533064e0f2f2100d7cb6fc22'/>
<id>078726ce6d56a767533064e0f2f2100d7cb6fc22</id>
<content type='text'>
Make spi core calculate the message length while
populating the other transfer parameters.

Usecase, driver can use it to populate framelength filed in their
controller.

Signed-off-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Make spi core calculate the message length while
populating the other transfer parameters.

Usecase, driver can use it to populate framelength filed in their
controller.

Signed-off-by: Sourav Poddar &lt;sourav.poddar@ti.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: Support transfer speed checking in the core</title>
<updated>2013-07-15T10:34:51+00:00</updated>
<author>
<name>Mark Brown</name>
<email>broonie@linaro.org</email>
</author>
<published>2013-07-10T13:57:26+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=a2fd4f9fa3b9f051550b36c4dfa74bc32bda24ee'/>
<id>a2fd4f9fa3b9f051550b36c4dfa74bc32bda24ee</id>
<content type='text'>
Allow drivers to avoid implementing their own checks for simple rates by
specifying the limits in the master structure.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Allow drivers to avoid implementing their own checks for simple rates by
specifying the limits in the master structure.

Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
<entry>
<title>spi: fix incorrect handling of min param in SPI_BPW_RANGE_MASK</title>
<updated>2013-06-01T18:46:16+00:00</updated>
<author>
<name>Stephen Warren</name>
<email>swarren@nvidia.com</email>
</author>
<published>2013-05-30T15:59:40+00:00</published>
<link rel='alternate' type='text/html' href='https://git.tavy.me/linux-stable.git/commit/?id=eca8960a8e0f48dc62c1063bcc33a626455d766e'/>
<id>eca8960a8e0f48dc62c1063bcc33a626455d766e</id>
<content type='text'>
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.

However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
SPI_BPW_RANGE_MASK is intended to work by calculating two masks; one
representing support for all bits up-to-and-including the "max" supported
value, and one representing support for all bits up-to-but-not-including
the "min" supported value, and then taking the difference between the
two, resulting in a mask representing support for all bits between
(inclusive) the min and max values.

However, the second mask ended up representing all bits up-to-and-
including rather up-to-but-not-including. Fix this bug.

Signed-off-by: Stephen Warren &lt;swarren@nvidia.com&gt;
Signed-off-by: Mark Brown &lt;broonie@linaro.org&gt;
</pre>
</div>
</content>
</entry>
</feed>
