linux-stable.git/include/linux/intel-gtt.h, branch linux-2.6.35.y Linux kernel stable tree agp/intel: Fix cache control for Sandybridge 2010-10-29T04:51:44+00:00 Zhenyu Wang zhenyuw@linux.intel.com 2010-08-27T03:08:57+00:00 c4cf17f1e6a95168d479656d066c5b8324c16b06 commit f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 upstream. Sandybridge GTT has new cache control bits in PTE, which controls graphics page cache in LLC or LLC/MLC, so we need to extend the mask function to respect the new bits. And set cache control to always LLC only by default on Gen6. Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de> 
commit f8f235e5bbf4e61f3e0886a44afb1dc4cfe8f337 upstream.

Sandybridge GTT has new cache control bits in PTE, which controls
graphics page cache in LLC or LLC/MLC, so we need to extend the mask
function to respect the new bits.

And set cache control to always LLC only by default on Gen6.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>