linux-stable.git/include/linux/clk/tegra.h, branch linux-5.5.y

clk: tegra: Add missing stubs for the case of !CONFIG_PM_SLEEP

2019-11-11T13:53:05+00:00

The new CPUIDLE driver uses the Tegra's CLK API and that driver won't
strictly depend on CONFIG_PM_SLEEP, hence add the required stubs in
order to allow compiling of the new driver with the CONFIG_PM_SLEEP=n.

Signed-off-by: Dmitry Osipenko 
Signed-off-by: Thierry Reding

clk: tegra: Add Tegra20/30 EMC clock implementation

2019-11-11T13:01:22+00:00

A proper External Memory Controller clock rounding and parent selection
functionality is required by the EMC drivers, it is not available using
the generic clock implementation because only the Memory Controller driver
is aware of what clock rates are actually available for a particular
device. EMC drivers will have to register a Tegra-specific CLK-API
callback which will perform rounding of a requested rate. EMC clock users
won't be able to request EMC clock by getting -EPROBE_DEFER until EMC
driver is probed and the callback is set up.

The functionality is somewhat similar to the clk-emc.c which serves
Tegra124+ SoCs. The later HW generations support more parent clock sources
and the HW configuration / integration with the EMC drivers differs a tad
from the older gens, hence it's not really worth to try to squash
everything into a single source file.

Acked-by: Peter De Schrijver 
Signed-off-by: Dmitry Osipenko 
Acked-by: Stephen Boyd 
Signed-off-by: Thierry Reding

treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201

2019-05-30T18:29:52+00:00

Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms and conditions of the gnu general public license
  version 2 as published by the free software foundation this program
  is distributed in the hope it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  for more details you should have received a copy of the gnu general
  public license along with this program if not see http www gnu org
  licenses

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 228 file(s).

Signed-off-by: Thomas Gleixner 
Reviewed-by: Allison Randal 
Reviewed-by: Steve Winslow 
Reviewed-by: Richard Fontana 
Reviewed-by: Alexios Zavras 
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190528171438.107155473@linutronix.de
Signed-off-by: Greg Kroah-Hartman

clk: tegra: MBIST work around for Tegra210

2018-03-08T18:18:08+00:00

Tegra210 has a hw bug which can cause IP blocks to lock up when ungating a
domain. The reason is that the logic responsible for resetting the memory
built-in self test mode can come up in an undefined state because its
clock is gated by a second level clock gate (SLCG). Work around this by
making sure the logic will get some clock edges by ensuring the relevant
clock is enabled and temporarily override the relevant SLCGs.
Unfortunately for some IP blocks, the control bits for overriding the
SLCGs are not in CAR, but in the IP block itself. This means we need to
map a few extra register banks in the clock code.

Signed-off-by: Peter De Schrijver 
Reviewed-by: Jon Hunter 
Tested-by: Jon Hunter 
Tested-by: Hector Martin 
Tested-by: Andre Heider 
Tested-by: Mikko Perttunen 
Signed-off-by: Thierry Reding 

fixup mbist

clk: tegra: Add SATA seq input control

2017-03-20T13:26:03+00:00

This will be used by the powergating driver to ensure proper sequencer
state when the SATA domain is powergated.

Signed-off-by: Peter De Schrijver 
Signed-off-by: Thierry Reding

clk: tegra: Handle UTMIPLL IDDQ

2017-03-20T13:09:05+00:00

Export UTMIPLL IDDQ functions. These will be needed when powergating the
XUSB partition.

Signed-off-by: BH Hsieh 
Signed-off-by: Peter De Schrijver 
Signed-off-by: Thierry Reding

clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs

2016-04-28T10:41:44+00:00

On Tegra210, hardware control of the SATA and XUSB pad PLLs must be
done during the UPHY enable sequence rather than the PLLE enable
sequence.  Export functions to do this so that hardware control can
be enabled from the XUSB padctl driver.

Signed-off-by: Andrew Bresticker 
Signed-off-by: Rhyland Klein 
Signed-off-by: Thierry Reding

clk: tegra: Properly include clk.h

2015-07-20T18:11:17+00:00

Clock provider drivers generally shouldn't include clk.h because
it's the consumer API. Only include clk.h in files that are using
it. Also add in a clkdev.h include that was missing in a file
using clkdev APIs.

Cc: Peter De Schrijver 
Cc: Thierry Reding 
Signed-off-by: Stephen Boyd

clk: tegra: make tegra_clocks_apply_init_table() arch_initcall

2015-02-02T13:47:28+00:00

tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37cfd66c5dd8dd45490bd3ea6971117d ("clk: tegra: defer
application of init table") for why that is).  On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.

Signed-off-by: Peter De Schrijver 
[paul@pwsan.com: tweaked the commit message]
Signed-off-by: Paul Walmsley 
Signed-off-by: Paul Walmsley 
Cc: Thierry Reding 
Cc: Prashant Gaikwad 
Cc: Mike Turquette 
Cc: Stephen Boyd 
Cc: Stephen Warren 
Cc: Thierry Reding 
Cc: Alexandre Courbot

clk: tegra: remove legacy reset APIs

2013-12-11T23:45:07+00:00

Now that no code uses the custom Tegra module reset API, we can remove
its implementation.

Signed-off-by: Stephen Warren 
Reviewed-by: Thierry Reding 
Acked-By: Peter De Schrijver