linux-stable.git/include/linux/clk-provider.h, branch v3.11.2

clk: gate: add CLK_GATE_HIWORD_MASK

2013-06-16T03:23:53+00:00

In Rockchip Cortex-A9 based chips, they don't use paradigm of
reading-changing-writing the register contents.  Instead they
use a hiword mask to indicate the changed bits.

When b1 should be set as gate, it also needs to indicate the change
by setting hiword mask (b1 << 16).

The patch adds gate flag for this usage.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Haojian Zhuang 
Signed-off-by: Mike Turquette

clk: divider: add CLK_DIVIDER_HIWORD_MASK flag

2013-06-16T03:23:49+00:00

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as setting divider, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds divider flag for this usage.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Haojian Zhuang 
Signed-off-by: Mike Turquette

clk: mux: add CLK_MUX_HIWORD_MASK

2013-06-16T03:23:36+00:00

In both Hisilicon & Rockchip Cortex-A9 based chips, they don't use the
paradigm of reading-changing-writing the register contents.
Instead they use a hiword mask to indicate the changed bits.

When b01 should be set as switching mux, it also needs to indicate
the change by setting hiword mask (b11 << 16).

The patch adds mux flag for this usage.

Signed-off-by: Heiko Stuebner 
Signed-off-by: Haojian Zhuang 
Signed-off-by: Mike Turquette

clk: add non CONFIG_OF routines for clk-provider

2013-05-29T05:52:46+00:00

Some drivers that are shared between architectures have HAVE_CLK selected
but don't have OF. To remove compilation errors for drivers that provide
clocks on DT with of_clk_add_provider we would have to enclose these calls
within #ifdef CONFIG_OF, #endif.

This patch adds some stubs for OF related clk-provider functions that
either do nothing or return appropriate values if CONFIG_OF is not set.
So, definition of these routines will always be available.

Signed-off-by: Sebastian Hesselbarth 
Acked-by: Arnd Bergmann 
Signed-off-by: Mike Turquette

clk: composite: rename 'div' references to 'rate'

2013-04-12T18:22:35+00:00

Rename all div_hw and div_ops related variables and functions to use
rate_hw, rate_ops, etc.  This is to make the rate-change portion of the
composite clk implementation more generic.  A patch following this one
will allow for fixed-rate clocks to reuse this infrastructure.

Signed-off-by: Mike Turquette 
Reviewed-by: Prashant Gaikwad 
Tested-by: Emilio López 
Cc: Gregory CLEMENT

clk: add device tree fixed-factor-clock binding support

2013-04-12T17:52:23+00:00

Add support for DT "fixed-factor-clock" binding to the common fixed
factor clock support.

Signed-off-by: Gregory CLEMENT 
Tested-by: Christian Ruppert 
Signed-off-by: Mike Turquette

clk: divider: Introduce CLK_DIVIDER_ALLOW_ZERO flag

2013-04-03T19:56:30+00:00

Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.

Signed-off-by: Soren Brinkmann 
Signed-off-by: Mike Turquette

clk: fix clk_mux::flags kerneldoc

2013-04-02T23:50:26+00:00

The kerneldoc comment for struct clk_mux documented the non-existent
num_clks instead of flags. Correct this.

Signed-off-by: James Hogan 
Signed-off-by: Mike Turquette

clk: Add composite clock type

2013-03-26T19:51:48+00:00

Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.

For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.

Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.

Signed-off-by: Prashant Gaikwad 
Signed-off-by: Mike Turquette

clk: add table lookup to mux

2013-03-22T22:18:18+00:00

Add a table lookup feature to the mux clock. Also allow arbitrary masks
instead of the width. This will be used by some clocks on Tegra114. Also
adapt the tegra periph clk because it uses struct clk_mux directly.

Signed-off-by: Peter De Schrijver 
Tested-by: Stephen Warren 
Signed-off-by: Mike Turquette