linux-stable.git/include/asm-powerpc, branch linux-2.6.23.y

Disable G5 NAP mode during SMU commands on U3

2008-02-26T00:14:08+00:00

patch 592a607bbc053bc6f614a0e619326009f4b3829e in mainline.

It appears that with the U3 northbridge, if the processor is in NAP
mode the whole time while waiting for an SMU command to complete,
then the SMU will fail.  It could be related to the weird backward
mechanism the SMU uses to get to system memory via i2c to the
northbridge that doesn't operate properly when the said bridge is
in napping along with the CPU.  That is on U3 at least, U4 doesn't
seem to be affected.

This didn't show before NO_HZ as the timer wakeup was enough to make
it work it seems, but that is no longer the case.

This fixes it by disabling NAP mode on those machines while
an SMU command is in flight.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras 
Signed-off-by: Greg Kroah-Hartman

POWERPC: Change fallocate to match unistd.h on powerpc

2008-02-08T20:01:18+00:00

patch f2205fbb5a8933514fd343cc329df631802b4543 in mainline.

Fix the fallocate system call on powerpc to match its unistd.h.

This implies none of these system calls are currently working with the
unistd.h sys call values:
	fallocate
	signalfd
	timerfd
	eventfd
	sync_file_range2

Signed-off-by: Patrick Mansfield 
Acked-by: Anton Blanchard 
Signed-off-by: Paul Mackerras 
Signed-off-by: Greg Kroah-Hartman

[POWERPC] Fix timekeeping on PowerPC 601

2007-09-19T05:26:34+00:00

Recent changes to the timekeeping code broke support for the PowerPC 601
processor which doesn't have the usual timebase facility but a slightly
different thing called (yuck) the RTC.

This fixes it, boot tested on an old 601 based PowerMac 7200.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] cell/PS3: Fix a bug that causes the PS3 to hang on the SPU Class 0 interrupt.

2007-09-10T18:30:36+00:00

The Cell BE Architecture spec states that the SPU MFC Class 0 interrupt
is edge-triggered.  The current spu interrupt handler assumes this
behavior and does not clear the interrupt status.

The PS3 hypervisor visualizes all SPU interrupts as level, and on return
from the interrupt handler the hypervisor will deliver a new virtual
interrupt for any unmasked interrupts which for which the status has not
been cleared.  This fix clears the interrupt status in the interrupt
handler.

Signed-off-by: Masato Noguchi 
Signed-off-by: Geoff Levand 
Signed-off-by: Jeremy Kerr 
Acked-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] Fix FSL BookE machine check reporting

2007-08-17T18:22:28+00:00

Reserved MCSR bits on FSL BookE parts may have spurious values
when mcheck occurs.  Mask these off when printing the MCSR to
avoid confusion.  Also, get rid of the MCSR_GL_CI bit defined
for e500 - this bit doesn't actually have any meaning.

Signed-off-by: Becky Bruce 
Signed-off-by: Kumar Gala

[POWERPC] Fix initialization and usage of dma_mask

2007-08-10T11:04:42+00:00

powerpc has a couple of bugs in the usage of dma_masks that tend to
break when drivers explicitly try to set a 32-bit mask for example.

First, the code that generates the pci devices from the OF device-tree
doesn't initialize the mask properly, then our implementation of
set_dma_mask() was trying to validate the -previous- mask value, not the
one passed in as an argument.

This fixes these problems.

Signed-off-by: Benjamin Herrenschmidt 
Signed-off-by: Paul Mackerras

[POWERPC] cell: Move SPU affinity init to spu_management_of_ops

2007-08-10T11:04:21+00:00

This patch moves affinity initialization code from spu_base.c to a
new spu_management_of_ops function (init_affinity), which is empty
in the case of PS3. This fixes a linking problem that was happening
when compiling for PS3.
Also, some small code style changes were made.

Signed-off-by: Andre Detsch 
Signed-off-by: Geoff Levand 
Acked-by: Arnd Bergmann 
Signed-off-by: Paul Mackerras

[POWERPC] Fixes for the SLB shadow buffer code

2007-08-03T09:36:01+00:00

On a machine with hardware 64kB pages and a kernel configured for a
64kB base page size, we need to change the vmalloc segment from 64kB
pages to 4kB pages if some driver creates a non-cacheable mapping in
the vmalloc area.  However, we never updated with SLB shadow buffer.
This fixes it.  Thanks to paulus for finding this.

Also added some write barriers to ensure the shadow buffer contents
are always consistent.

Signed-off-by: Michael Neuling 
Signed-off-by: Paul Mackerras

[POWERPC] Expand RPN field to 34 bits when using 64k pages

2007-08-03T04:08:24+00:00

The real page number field in our PTEs when configured for 64kB pages
is currently 32 bits, which turns out to be not quite enough for the
resources that the eHCA driver wants to map.  This expands the RPN
field to include 2 adjacent, previously-unused bits.

Signed-off-by: Paul Mackerras 
Acked-by: Benjamin Herrenschmidt

Fix WARN_ON() on bitfield ops

2007-08-01T04:12:07+00:00

Alexey Dobriyan noticed that the new WARN_ON() semantics that were
introduced by commit 684f978347deb42d180373ac4c427f82ef963171 (to also
return the value to be warned on) didn't compile when given a bitfield,
because the typeof doesn't work for bitfields.

So instead of the typeof trick, use an "int" variable together with a
"!!(x)" expression, as suggested by Al Viro.

To make matters more interesting, Paul Mackerras points out that that is
sub-optimal on Power, but the old asm-coded comparison seems to be buggy
anyway on 32-bit Power if the conditional was 64-bit, so I think there
are more problems there.

Regardless, the new WARN_ON() semantics may have been a bad idea.  But
this at least avoids the more serious complications.

Cc: Alexey Dobriyan 
Cc: Herbert Xu 
Cc: Paul Mackerras 
Cc: Al Viro 
Cc: Ingo Molnar 
Cc: Andrew Morton 
Signed-off-by: Linus Torvalds