linux-stable.git/drivers/vme, branch v3.18.136

vme: ca91cx42: fix LM_CTL address mask

2018-12-17T09:07:12+00:00

commit 5a2f8831243337dd05df42174b4d7b1e01daacda upstream.

Universe II datasheet defines following address space values
for LM_CTL[16:18]

000=A16
001=A24
010=A32
011,100,101=Reserved
110=User1
111=User2

Mask 5<<16 is not the right one for matching [16:18], instead we should
use 7<<16.

Signed-off-by: Dmitry Kalinkin 
Cc: Igor Alekseev 
Reported-by: Dan Carpenter 
Signed-off-by: Greg Kroah-Hartman

vme: Fix wrong pointer utilization in ca91cx42_slave_get

2018-12-17T09:07:12+00:00

commit c8a6a09c1c617402cc9254b2bc8da359a0347d75 upstream.

In ca91cx42_slave_get function, the value pointed by vme_base pointer is
set through:

*vme_base = ioread32(bridge->base + CA91CX42_VSI_BS[i]);

So it must be dereferenced to be used in calculation of pci_base:

*pci_base = (dma_addr_t)*vme_base + pci_offset;

This bug was caught thanks to the following gcc warning:

drivers/vme/bridges/vme_ca91cx42.c: In function ‘ca91cx42_slave_get’:
drivers/vme/bridges/vme_ca91cx42.c:467:14: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast]
*pci_base = (dma_addr_t)vme_base + pci_offset;

Signed-off-by: Augusto Mecking Caringi 
Acked-By: Martyn Welch 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman

vme: bridges: use pci_zalloc_consistent

2014-08-08T22:57:30+00:00

Remove the now unnecessary memset too.

Signed-off-by: Joe Perches 
Cc: Martyn Welch 
Cc: Manohar Vanga 
Acked-by: Greg Kroah-Hartman 
Signed-off-by: Andrew Morton 
Signed-off-by: Linus Torvalds

VME: remove duplicate CA91CX42_DCTL_VDW_M define

2014-07-09T23:33:42+00:00

The CA91CX42_DCTL_VDW_M define is cut and pasted twice so we can delete
the second instance.

Signed-off-by: Dan Carpenter 
Signed-off-by: Greg Kroah-Hartman

vme_tsi148: Utilize to_pci_dev() macro

2014-04-16T21:08:37+00:00

Save some characters by using to_pci_dev() instead of container_of().

Signed-off-by: Aaron Sierra 
Signed-off-by: Greg Kroah-Hartman

vme_tsi148: Fix PCI address mapping assumption

2014-04-16T21:08:37+00:00

Previously, tsi148_master_set() assumed the address contained in its
PCI bus resource represented the actual PCI bus address. This is a fine
assumption on some platforms. However, on platforms that don't use a
1:1 (CPU:PCI) mapping this results in the tsi148 driver configuring an
invalid master window translation.

This patch updates the vme_tsi148 driver to first convert the address
contained in the PCI bus resource into a PCI bus address before using
it.

[asierra: account for pcibios_resource_to_bus() prototype change]
Signed-off-by: Joe Schultz 
Signed-off-by: Aaron Sierra 
Signed-off-by: Greg Kroah-Hartman

vme_tsi148: Fix typo in tsi148_slave_get()

2014-04-16T21:08:37+00:00

This patch corrects a typo where "vme_base" was used instead of
"*vme_base". The typo resulted in an incorrect value being returned
to userspace (via vme_user).

It also removes the following compile warning on some platforms:

warning: cast from pointer to integer of different size

[asierra: commit title/log rewording]
Signed-off-by: Joe Schultz 
Signed-off-by: Aaron Sierra 
Signed-off-by: Greg Kroah-Hartman

Merge 3.14-rc3 into char-misc-next

2014-02-18T16:09:40+00:00

We need the fixes here for future mei and other patches.

Signed-off-by: Greg Kroah-Hartman

VME: Stop using memcpy_[to|from]io() due to unwanted behaviour

2014-02-15T19:53:39+00:00

The ca91cx42 and tsi148 VME bridges use the width of reads and writes on the
PCI bus in part to control the width of the cycles on the VME bus. It is
important that we can control the width of cycles on the VME bus as some VME
hardware requires cycles of a specific width. The memcpy_toio() and
memcpy_fromio() functions do not provide sufficient control, so instead loop
using ioread functions.

Reported-by: Michael Kenney 
Signed-off-by: Martyn Welch 
Signed-off-by: Greg Kroah-Hartman

VME: Correct read/write alignment algorithm

2014-02-07T16:16:14+00:00

In order to ensure the correct width cycles on the VME bus, the VME bridge
drivers implement an algorithm to utilise the largest possible width reads and
writes whilst maintaining natural alignment constraints. The algorithm
currently looks at the start address rather than the current read/write address
when determining whether a 16-bit width cycle is required to get to 32-bit
alignment.  This results in incorrect alignment,

Reported-by: Jim Strouth 
Tested-by: Jim Strouth 
Signed-off-by: Martyn Welch 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman