linux-stable.git/drivers/usb/Kconfig, branch linux-3.2.y

Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus

2011-11-03T20:28:14+00:00

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (37 commits)
  MIPS: O32: Provide definition of registers ta0 .. ta3.
  MIPS: perf: Add Octeon support for hardware perf.
  MIPS: perf: Add support for 64-bit perf counters.
  MIPS: perf: Reorganize contents of perf support files.
  MIPS: perf: Cleanup formatting in arch/mips/kernel/perf_event.c
  MIPS: Add accessor macros for 64-bit performance counter registers.
  MIPS: Add probes for more Octeon II CPUs.
  MIPS: Add more CPU identifiers for Octeon II CPUs.
  MIPS: XLR, XLS: Add comment for smp setup
  MIPS: JZ4740: GPIO: Check correct IRQ in demux handler
  MIPS: JZ4740: GPIO: Simplify IRQ demuxer
  MIPS: JZ4740: Use generic irq chip
  MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines
  MIPS: Alchemy: kill au1xxx.h header
  MIPS: Alchemy: clean DMA code of CONFIG_SOC_AU1??? defines
  MIPS, IDE: Alchem, au1xxx-ide: Remove pb1200/db1200 header dep
  MIPS: Alchemy: Redo PCI as platform driver
  MIPS: Alchemy: more base address cleanup
  MIPS: Alchemy: rewrite USB platform setup.
  MIPS: Alchemy: abstract USB block control register access
  ...

Fix up trivial conflicts in:
	arch/mips/alchemy/devboards/db1x00/platform.c
	drivers/ide/Kconfig
	drivers/mmc/host/au1xmmc.c
	drivers/video/Kconfig
	sound/mips/Kconfig

MIPS: Alchemy: remove all CONFIG_SOC_AU1??? defines

2011-10-24T22:34:24+00:00

Now that no driver any longer depends on the CONFIG_SOC_AU1???  symbols,
it's time to get rid of them: Move some of the platform devices to the
boards which can use them, Rename a few (unused) constants in the header,
Replace them with MIPS_ALCHEMY in the various Kconfig files.  Finally
delete them altogether from the Alchemy Kconfig file.

Signed-off-by: Manuel Lauss 
To: Linux-MIPS 
Patchwork: https://patchwork.linux-mips.org/patch/2707/
Signed-off-by: Ralf Baechle

USB: Fix USB Kconfig dependency problem on 85xx/QoirQ platforms

2011-10-18T20:51:33+00:00

For FSL PPC SoCs USB_ARCH_HAS_EHCI currently on depends on PPC_83xx.
However that excludes support for USB on 85xx & QorIQ devices.  Use
FSL_SOC insted which will get us 83xx, 85xx, QorIQ, and 5xxx which all
have the same USB IP on them.

Signed-off-by: Xulei 
Signed-off-by: Kumar Gala 
Signed-off-by: Greg Kroah-Hartman

usb/host: introduce USB_ARCH_HAS_XHCI

2011-09-26T22:51:11+00:00

to make it look like OHCI and EHCI, we introduce
that symbol and USB_XHCI_HCD depend on that
instead of PCI.

[bigeasy@linutronix.de: wire up USB_ARCH_HAS_HCD]

Signed-off-by: Felipe Balbi 
Signed-off-by: Sebastian Andrzej Siewior 
Signed-off-by: Sarah Sharp 
Signed-off-by: Greg Kroah-Hartman

usb: Provide usb_speed_string() function

2011-09-18T08:29:04+00:00

In a few places in the kernel, the code prints
a human-readable USB device speed (eg. "high speed").
This involves a switch statement sometimes wrapped
around in ({ ... }) block leading to code repetition.

To mitigate this issue, this commit introduces
usb_speed_string() function, which returns
a human-readable name of provided speed.

It also changes a few places switch was used to use
this new function.  This changes a bit the way the
speed is printed in few instances at the same time
standardising it.

Signed-off-by: Michal Nazarewicz 
Signed-off-by: Greg Kroah-Hartman

usb: Introduce DesignWare USB3 DRD Driver

2011-08-22T23:03:11+00:00

The DesignWare USB3 is a highly
configurable IP Core which can be
instantiated as Dual-Role Device (DRD),
Peripheral Only and Host Only (XHCI)
configurations.

Several other parameters can be configured
like amount of FIFO space, amount of TX and
RX endpoints, amount of Host Interrupters,
etc.

The current driver has been validated with
a virtual model of version 1.73a of that core
and with an FPGA burned with version 1.83a
of the DRD core. We have support for PCIe
bus, which is used on FPGA prototyping, and
for the OMAP5, more adaptation (or glue)
layers can be easily added and the driver
is half prepared to handle any possible
configuration the HW engineer has chosen
considering we have the information on
one of the GHWPARAMS registers to do
runtime checking of certain features.

More runtime checks can, and should, be added
in order to make this driver even more flexible
with regards to number of endpoints, FIFO sizes,
transfer types, etc.

While this supports only the device side, for
now, we will add support for Host side (xHCI -
see the updated series Sebastian has sent [1])
and OTG after we have it all stabilized.

[1] http://marc.info/?l=linux-usb&m=131341992020339&w=2

Signed-off-by: Felipe Balbi 
Signed-off-by: Greg Kroah-Hartman

USB: pxa168: Add onchip USB host controller support

2011-08-22T22:38:30+00:00

- Add EHCI Host controller driver
- Add wrapper that creates resources for host controller driver

v2 - Call clk_put() after clk_disable() in probe function

Signed-off-by: Tanmay Upadhyay 
Signed-off-by: Greg Kroah-Hartman

USB: EHCI: Add bus glue for GRLIB GRUSBHC controller

2011-05-03T18:43:48+00:00

This patch adds support for the GRLIB GRUSBHC EHCI controller from
Aeroflex Gaisler. The controller is typically found on LEON/GRLIB
SoCs.

Tested on GR-LEON4-ITX with with little endian interface and on
LEON3 system on GR-PCI-XC5V development board for big endian
controller.

Signed-off-by: Jan Andersson 
Signed-off-by: Greg Kroah-Hartman

Merge 2.6.39-rc4 into usb-next

2011-04-19T12:50:38+00:00

This is needed to help resolve some xhci issues and other minor
differences.

Signed-off-by: Greg Kroah-Hartman

USB: Add initial S5P EHCI driver

2011-04-13T23:50:52+00:00

This patch adds host USB high speed driver for samsung S5P series. This
is initial driver and we need additional implementation to support some
functions like power management.

Signed-off-by: Jingoo Han 
Signed-off-by: Joonyoung Shim 
Signed-off-by: Greg Kroah-Hartman