linux-stable.git/drivers/tty/serial, branch v3.18.46

serial: samsung: Fix ERR pointer dereference on deferred probe

2016-08-22T16:23:00+00:00

[ Upstream commit e51e4d8a185de90424b03f30181b35f29c46a25a ]

When the clk_get() of "uart" clock returns EPROBE_DEFER, the next re-probe
finishes with success but uses invalid (ERR_PTR) values.  This leads to
dereferencing of ERR_PTR stored under ourport->clk:

	12c30000.serial: Controller clock not found
	(...)
	12c30000.serial: ttySAC3 at MMIO 0x12c30000 (irq = 61, base_baud = 0) is a S3C6400/10
	Unable to handle kernel paging request at virtual address fffffdfb

	(clk_prepare) from [] (s3c24xx_serial_pm+0x20/0x128)
	(s3c24xx_serial_pm) from [] (uart_change_pm+0x38/0x40)
	(uart_change_pm) from [] (uart_add_one_port+0x31c/0x44c)
	(uart_add_one_port) from [] (s3c24xx_serial_probe+0x2a8/0x418)
	(s3c24xx_serial_probe) from [] (platform_drv_probe+0x50/0xb0)
	(platform_drv_probe) from [] (driver_probe_device+0x1f4/0x2b0)
	(driver_probe_device) from [] (bus_for_each_drv+0x44/0x8c)
	(bus_for_each_drv) from [] (__device_attach+0x9c/0x100)
	(__device_attach) from [] (bus_probe_device+0x84/0x8c)
	(bus_probe_device) from [] (deferred_probe_work_func+0x60/0x8c)
	(deferred_probe_work_func) from [] (process_one_work+0x120/0x328)
	(process_one_work) from [] (worker_thread+0x2c/0x4ac)
	(worker_thread) from [] (kthread+0xd8/0xf4)
	(kthread) from [] (ret_from_fork+0x14/0x3c)

The first unsuccessful clk_get() causes s3c24xx_serial_init_port() to
exit with failure but the s3c24xx_uart_port is left half-configured
(e.g. port->mapbase is set, clk contains ERR_PTR).  On next re-probe,
the function s3c24xx_serial_init_port() will exit early with success
because of configured port->mapbase and driver will use old values,
including the ERR_PTR as clock.

Fix this by cleaning the port->mapbase on error path so each re-probe
will initialize all of the port settings.

Fixes: 60e93575476f ("serial: samsung: enable clock before clearing pending interrupts during init")
Cc: 
Signed-off-by: Krzysztof Kozlowski 
Reviewed-by: Javier Martinez Canillas 
Tested-by: Javier Martinez Canillas 
Tested-by: Kevin Hilman 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: samsung: Reorder the sequence of clock control when call s3c24xx_serial_set_termios()

2016-07-12T12:48:18+00:00

[ Upstream commit b8995f527aac143e83d3900ff39357651ea4e0f6 ]

This patch fixes the broken serial log when changing the clock source
of uart device. Before disabling the original clock source, this patch
enables the new clock source to protect the clock off state for a split second.

Signed-off-by: Chanwoo Choi 
Reviewed-by: Marek Szyprowski 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

8250: use callbacks to access UART_DLL/UART_DLM

2016-07-12T12:47:21+00:00

[ Upstream commit 0b41ce991052022c030fd868e03877700220b090 ]

Some UART HW has a single register combining UART_DLL/UART_DLM
(this was probably forgotten in the change that introduced the
callbacks, commit b32b19b8ffc05cbd3bf91c65e205f6a912ca15d9)

Fixes: b32b19b8ffc0 ("[SERIAL] 8250: set divisor register correctly ...")

Signed-off-by: Sebastian Frias 
Reviewed-by: Peter Hurley 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

QE-UART: add "fsl,t1040-ucc-uart" to of_device_id

2016-06-03T15:30:32+00:00

[ Upstream commit 11ca2b7ab432eb90906168c327733575e68d388f ]

New bindings use "fsl,t1040-ucc-uart" as the compatible for qe-uart.
So add it.

Signed-off-by: Zhao Qiang 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

tty: Add support for PCIe WCH382 2S multi-IO card

2016-03-02T20:19:13+00:00

[ Upstream commit 7dde55787b43a8f2b4021916db38d90c03a2ec64 ]

WCH382 2S board is a PCIe card with 2 DB9 COM ports detected as
Serial controller: Device 1c00:3253 (rev 10) (prog-if 05 [16850])

Signed-off-by: Jeremy McNicoll 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

tty: Add support for the WCH384 4S multi-IO card

2016-03-02T20:19:08+00:00

[ Upstream commit 72a3c0e4e6624a77ee6eee0903f209185fe20647 ]

WCH384 4S board is a PCI-E card with 4 DB9 COM ports detected as
Serial controller: Device 1c00:3470 (rev 10) (prog-if 05 [16850])

Signed-off-by: Sergej Pupykin 
Acked-by: Zany Yan 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

parport: Add support for the WCH382 2S/1P multi-IO card

2016-03-02T20:19:08+00:00

[ Upstream commit 2fdd8c8c5304901fa7dbb2ce5dbc90a1984cee3d ]

WCH382 is a PCI-E card with 1 LPT and 2 DB9 COM ports detected as
Serial controller: Device 1c00:3250 (rev 10) (prog-if 05 [16850])

Signed-off-by: Sergej Pupykin 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add Intel Broadwell ports

2016-02-15T20:42:34+00:00

[ Upstream commit 6c55d9b98335f7f6bd5f061866ff1633401f3a44 ]

Some recent (early 2015) macbooks have Intel Broadwell where LPSS UARTs are
PCI enumerated instead of ACPI. The LPSS UART block is pretty much same as
used on Intel Baytrail so we can reuse the existing Baytrail setup code.

Add both Broadwell LPSS UART ports to the list of supported devices.

Signed-off-by: Leif Liddy 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Heikki Krogerus 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add support for 12 port Exar boards

2015-11-15T17:51:53+00:00

[ Upstream commit be32c0cf0462c36f482b5ddcff1d8371be1e183c ]

The Exar XR17V358 can also be combined with a XR17V354 chip to act as a
single 12 port chip. This works the same way as the combining two XR17V358
chips. But the reported device id then is 0x4358.

Signed-off-by: Soeren Grunewald 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add support for 16 port Exar boards

2015-11-15T17:51:53+00:00

[ Upstream commit 96a5d18bc1338786fecac73599f1681f59a59a8e ]

The Exar XR17V358 chip usually provides only 8 ports. But two chips can be
combined to act as a single 16 port chip. Therefor one chip is configured
as master the second as slave by connecting the mode pin to VCC (master)
or GND (slave).

Then the master chip is reporting a different device-id depending on
whether a slave is detected or not. The UARTs 8-15 are addressed from
0x2000-0x3fff. So the offset of 0x400 from UART to UART can be used to
address all 16 ports as before.

See: https://www.exar.com/common/content/document.ashx?id=1587 page 11

Signed-off-by: Soeren Grunewald 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin