linux-stable.git/drivers/tty/serial, branch v3.18.35

QE-UART: add "fsl,t1040-ucc-uart" to of_device_id

2016-06-03T15:30:32+00:00

[ Upstream commit 11ca2b7ab432eb90906168c327733575e68d388f ]

New bindings use "fsl,t1040-ucc-uart" as the compatible for qe-uart.
So add it.

Signed-off-by: Zhao Qiang 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

tty: Add support for PCIe WCH382 2S multi-IO card

2016-03-02T20:19:13+00:00

[ Upstream commit 7dde55787b43a8f2b4021916db38d90c03a2ec64 ]

WCH382 2S board is a PCIe card with 2 DB9 COM ports detected as
Serial controller: Device 1c00:3253 (rev 10) (prog-if 05 [16850])

Signed-off-by: Jeremy McNicoll 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

tty: Add support for the WCH384 4S multi-IO card

2016-03-02T20:19:08+00:00

[ Upstream commit 72a3c0e4e6624a77ee6eee0903f209185fe20647 ]

WCH384 4S board is a PCI-E card with 4 DB9 COM ports detected as
Serial controller: Device 1c00:3470 (rev 10) (prog-if 05 [16850])

Signed-off-by: Sergej Pupykin 
Acked-by: Zany Yan 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

parport: Add support for the WCH382 2S/1P multi-IO card

2016-03-02T20:19:08+00:00

[ Upstream commit 2fdd8c8c5304901fa7dbb2ce5dbc90a1984cee3d ]

WCH382 is a PCI-E card with 1 LPT and 2 DB9 COM ports detected as
Serial controller: Device 1c00:3250 (rev 10) (prog-if 05 [16850])

Signed-off-by: Sergej Pupykin 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add Intel Broadwell ports

2016-02-15T20:42:34+00:00

[ Upstream commit 6c55d9b98335f7f6bd5f061866ff1633401f3a44 ]

Some recent (early 2015) macbooks have Intel Broadwell where LPSS UARTs are
PCI enumerated instead of ACPI. The LPSS UART block is pretty much same as
used on Intel Baytrail so we can reuse the existing Baytrail setup code.

Add both Broadwell LPSS UART ports to the list of supported devices.

Signed-off-by: Leif Liddy 
Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Heikki Krogerus 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add support for 12 port Exar boards

2015-11-15T17:51:53+00:00

[ Upstream commit be32c0cf0462c36f482b5ddcff1d8371be1e183c ]

The Exar XR17V358 can also be combined with a XR17V354 chip to act as a
single 12 port chip. This works the same way as the combining two XR17V358
chips. But the reported device id then is 0x4358.

Signed-off-by: Soeren Grunewald 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250_pci: Add support for 16 port Exar boards

2015-11-15T17:51:53+00:00

[ Upstream commit 96a5d18bc1338786fecac73599f1681f59a59a8e ]

The Exar XR17V358 chip usually provides only 8 ports. But two chips can be
combined to act as a single 16 port chip. Therefor one chip is configured
as master the second as slave by connecting the mode pin to VCC (master)
or GND (slave).

Then the master chip is reporting a different device-id depending on
whether a slave is detected or not. The UARTs 8-15 are addressed from
0x2000-0x3fff. So the offset of 0x400 from UART to UART can be used to
address all 16 ports as before.

See: https://www.exar.com/common/content/document.ashx?id=1587 page 11

Signed-off-by: Soeren Grunewald 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: 8250: don't bind to SMSC IrCC IR port

2015-10-28T02:14:43+00:00

[ Upstream commit ffa34de03bcfbfa88d8352942bc238bb48e94e2d ]

SMSC IrCC SIR/FIR port should not be bound to by
(legacy) serial driver so its own driver (smsc-ircc2)
can bind to it.

Signed-off-by: Maciej Szmigiero 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

tty/serial: at91: RS485 mode: 0 is valid for delay_rts_after_send

2015-07-12T14:54:24+00:00

[ Upstream commit 8687634b7908c42eb700e0469e110e02833611d1 ]

In RS485 mode, we may want to set the delay_rts_after_send value to 0.
In the datasheet, the 0 value is said to "disable" the Transmitter Timeguard but
this is exactly the expected behavior if we want no delay...

Moreover, if the value was set to non-zero value by device-tree or earlier
ioctl command, it was impossible to change it back to zero.

Reported-by: Sami Pietikäinen 
Signed-off-by: Nicolas Ferre 
Cc: stable@vger.kernel.org  # 3.2+
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin

serial: imx: Fix DMA handling for IDLE condition aborts

2015-07-03T16:34:44+00:00

[ Upstream commit 392bceedb107a3dc1d4287e63d7670d08f702feb ]

The driver configures the IDLE condition to interrupt the SDMA engine.
Since the SDMA UART ROM script doesn't clear the IDLE bit itself, this
caused repeated 1-byte DMA transfers, regardless of available data in the
RX FIFO. Also, when returning due to the IDLE condition, the UART ROM
script already increased its counter, causing residue to be off by one.

This patch clears the IDLE condition to avoid repeated 1-byte DMA transfers
and decreases count by when the DMA transfer was aborted due to the IDLE
condition, fixing serial transfers using DMA on i.MX6Q.

Reported-by: Peter Seiderer 
Signed-off-by: Philipp Zabel 
Tested-by: Fabio Estevam 
Cc: stable 
Signed-off-by: Greg Kroah-Hartman 
Signed-off-by: Sasha Levin