linux-stable.git/drivers/spi, branch v3.16.3

spi/pxa2xx: Add ACPI ID for Intel Braswell

2014-09-17T16:22:09+00:00

commit aca26364689e00e3b2052072424682231bdae6ae upstream.

The SPI host controller is the same as used in Baytrail, only the ACPI ID
is different so add this new ID to the list.

Signed-off-by: Alan Cox 
Signed-off-by: Mika Westerberg 
Signed-off-by: Mark Brown 
Signed-off-by: Greg Kroah-Hartman

spi: omap2-mcspi: Configure hardware when slave driver changes mode

2014-09-17T16:21:51+00:00

commit 97ca0d6cc118716840ea443e010cb3d5f2d25eaf upstream.

Commit id 2bd16e3e23d9df41592c6b257c59b6860a9cc3ea
(spi: omap2-mcspi: Do not configure the controller
on each transfer unless needed) does its job too
well so omap2_mcspi_setup_transfer() isn't called
even when an SPI slave driver changes 'spi->mode'.
The result is that the mode requested by the SPI
slave driver never takes effect.

Fix this by adding the 'mode' member to the
omap2_mcspi_cs structure which holds the mode
value that the hardware is configured for.
When the SPI slave driver changes 'spi->mode'
it will be different than the value of this new
member and the SPI master driver will know that
the hardware must be reconfigured (by calling
omap2_mcspi_setup_transfer()).

Fixes: 2bd16e3e23 (spi: omap2-mcspi: Do not configure the controller on each transfer unless needed)
Signed-off-by: Mark A. Greer 
Signed-off-by: Mark Brown 
Signed-off-by: Greg Kroah-Hartman

spi: orion: fix incorrect handling of cell-index DT property

2014-09-17T16:21:51+00:00

commit e06871cd2c92e5c65d7ca1d32866b4ca5dd4ac30 upstream.

In commit f814f9ac5a81 ("spi/orion: add device tree binding"), Device
Tree support was added to the spi-orion driver. However, this commit
reads the "cell-index" property, without taking into account the fact
that DT properties are big-endian encoded.

Since most of the platforms using spi-orion with DT have apparently
not used anything but cell-index = <0>, the problem was not
visible. But as soon as one starts using cell-index = <1>, the problem
becomes clearly visible, as the master->bus_num gets a wrong value
(actually it gets the value 0, which conflicts with the first bus that
has cell-index = <0>).

This commit fixes that by using of_property_read_u32() to read the
property value, which does the appropriate endianness conversion when
needed.

Fixes: f814f9ac5a81 ("spi/orion: add device tree binding")
Signed-off-by: Thomas Petazzoni 
Acked-by: Sebastian Hesselbarth 
Signed-off-by: Mark Brown 
Signed-off-by: Greg Kroah-Hartman

Merge remote-tracking branches 'spi/fix/pxa2xx', 'spi/fix/qup' and 'spi/fix/sh-sci' into spi-linus

2014-06-28T13:01:23+00:00

spi: qup: Remove chip select function

2014-06-22T10:48:09+00:00

This patch removes the chip select function.  Chip select should instead be
supported using GPIOs, defining the DT entry "cs-gpios", and letting the SPI
core assert/deassert the chip select as it sees fit.

The chip select control inside the controller is buggy.  It is supposed to
automatically assert the chip select based on the activity in the controller,
but it is buggy and doesn't work at all.  So instead we elect to use GPIOs.

Signed-off-by: Andy Gross 
Signed-off-by: Mark Brown

spi: qup: Fix order of spi_register_master

2014-06-21T10:11:54+00:00

This patch moves the devm_spi_register_master below the initialization of the
runtime_pm.  If done in the wrong order, the spi_register_master fails if any
probed slave devices issue SPI transactions.

Signed-off-by: Andy Gross 
Acked-by: Ivan T. Ivanov 
Signed-off-by: Mark Brown

spi: sh-sci: fix use-after-free in sh_sci_spi_remove()

2014-06-17T14:47:31+00:00

setbits() uses sp->membase.

Signed-off-by: Jürg Billeter 
Acked-by: Geert Uytterhoeven 
Signed-off-by: Mark Brown

spi/pxa2xx: fix incorrect SW mode chipselect setting for BayTrail LPSS SPI

2014-06-17T14:45:52+00:00

It was observed that after module removal followed by insertion,
the SW mode chipselect is not properly set. Thus causing transfer
failure due to incorrect CS toggling.

Signed-off-by: Chew, Chiau Ee 
Acked-by: Mika Westerberg 
Signed-off-by: Mark Brown

spi/pxa2xx: change default supported DMA burst size to 1

2014-06-06T09:52:46+00:00

This is to fix the SPI DMA transfer failure for speed less than 1M.
If using current DMA burst size setting (16), the Rx data bytes are
invalid due to each data byte is multiplied according to the burst
size setting.

Let's said supposedly we shall receive the following 18 bytes of data:
01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18
Instead, the data bytes received consist of "16 bytes of '01' +
2 bytes of '02'" :
01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 02 02

Signed-off-by: Chew, Chiau Ee 
Acked-by: Mika Westerberg 
Signed-off-by: Mark Brown

Merge remote-tracking branch 'spi/topic/workqueue' into spi-next

2014-06-02T16:08:43+00:00