linux-stable.git/drivers/spi/Makefile, branch v6.2

spi: wpcm-fiu: Add driver for Nuvoton WPCM450 Flash Interface Unit (FIU)

2022-11-25T13:30:15+00:00

The Flash Interface Unit (FIU) is the SPI flash controller in the
Nuvoton WPCM450 BMC SoC. It supports four chip selects, and direct
(memory-mapped) access to 16 MiB per chip. Larger flash chips can be
accessed by software-defined SPI transfers.

The FIU in newer NPCM7xx SoCs is not compatible with the WPCM450 FIU.

Signed-off-by: Jonathan Neuschäfer 
Link: https://lore.kernel.org/r/20221124191400.287918-3-j.neuschaefer@gmx.net
Signed-off-by: Mark Brown

spi: Add Socionext F_OSPI SPI flash controller driver

2022-11-24T11:05:07+00:00

Introduce Socionext F_OSPI controller driver. This controller is used to
communicate with slave devices such as SPI Flash memories. It supports
4 slave devices and up to 8-bit wide bus, but supports master mode only.

This driver uses spi-mem framework for SPI flash memory access, and
can only operate indirect access mode and single data rate mode.

Signed-off-by: Kunihiko Hayashi 
Link: https://lore.kernel.org/r/20221124003351.7792-3-hayashi.kunihiko@socionext.com
Signed-off-by: Mark Brown

spi: microchip: pci1xxxx: Add driver for SPI controller of PCI1XXXX PCIe switch

2022-10-17T11:49:48+00:00

Microchip pci1xxxx is a PCIe switch with a multi-function endpoint on one of its
downstream ports. SPI is one of the functions in the multi-function endpoint. This
function has 2 SPI masters, operates at a maximum frequency of 30 MHz and supports
7 client devices per master. This patch adds complete functionality to the SPI
function except for suspend and resume.

Signed-off-by: Tharun Kumar P 
Link: https://lore.kernel.org/r/20221006050514.115564-2-tharunkumar.pasumarthi@microchip.com
Signed-off-by: Mark Brown

spi: microchip-core-qspi: Add support for microchip fpga qspi controllers

2022-08-15T11:17:38+00:00

Add a driver for Microchip FPGA QSPI controllers. This driver also
supports "hard" QSPI controllers on Polarfire SoC.

Signed-off-by: Naga Sureshkumar Relli 
Reviewed-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220808064603.1174906-4-nagasuresh.relli@microchip.com
Signed-off-by: Mark Brown

spi: spi-gxp: Add support for HPE GXP SoCs

2022-07-29T16:38:52+00:00

The GXP supports 3 separate SPI interfaces to accommodate the system
flash, core flash, and other functions. The SPI engine supports variable
clock frequency, selectable 3-byte or 4-byte addressing and a
configurable x1, x2, and x4 command/address/data modes. The memory
buffer for reading and writing ranges between 256 bytes and 8KB. This
driver supports access to the core flash and bios part.

Signed-off-by: Nick Hawkins 
Link: https://lore.kernel.org/r/20220728161459.7738-2-nick.hawkins@hpe.com
Signed-off-by: Mark Brown

spi: add support for microchip fpga spi controllers

2022-06-07T12:57:07+00:00

Add a driver for Microchip FPGA SPI controllers, specifically
supporting the "hard" controllers on PolarFire SoC.

Co-developed-by: Daire McNamara 
Signed-off-by: Daire McNamara 
Signed-off-by: Conor Dooley 
Link: https://lore.kernel.org/r/20220607073833.2331539-2-conor.dooley@microchip.com
Signed-off-by: Mark Brown

spi: spi-mem: Convert Aspeed SMC driver to spi-mem

2022-05-16T11:59:15+00:00

This SPI driver adds support for the Aspeed static memory controllers
of the AST2600, AST2500 and AST2400 SoCs using the spi-mem interface.

 * AST2600 Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . Only supports SPI type flash memory
   . different segment register interface
   . single, dual and quad mode.

 * AST2600 SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . different segment register interface
   . single, dual and quad mode.

 * AST2500 Firmware SPI Memory Controller (FMC)
   . BMC firmware
   . 3 chip select pins (CE0 ~ CE2)
   . supports SPI type flash memory (CE0-CE1)
   . CE2 can be of NOR type flash but this is not supported by the driver
   . single, dual mode.

 * AST2500 SPI Flash Controller (SPI1 and SPI2)
   . host firmware
   . 2 chip select pins (CE0 ~ CE1)
   . single, dual mode.

 * AST2400 New Static Memory Controller (also referred as FMC)
   . BMC firmware
   . New register set
   . 5 chip select pins (CE0 ∼ CE4)
   . supports NOR flash, NAND flash and SPI flash memory.
   . single, dual and quad mode.

Each controller has a memory range on which flash devices contents are
mapped. Each device is assigned a window that can be changed at bootime
with the Segment Address Registers.

Each SPI flash device can then be accessed in two modes: Command and
User. When in User mode, SPI transfers are initiated with accesses to
the memory segment of a device. When in Command mode, memory
operations on the memory segment of a device generate SPI commands
automatically using a Control Register for the settings.

This initial patch adds support for User mode. Command mode needs a little
more work to check that the memory window on the AHB bus fits the device
size. It will come later when support for direct mapping is added.

Single and dual mode RX transfers are supported. Other types than SPI
are not supported.

Reviewed-by: Joel Stanley 
Tested-by: Joel Stanley 
Tested-by: Tao Ren 
Tested-by: Jae Hyun Yoo 
Signed-off-by: Chin-Ting Kuo 
Signed-off-by: Cédric Le Goater 
Link: https://lore.kernel.org/r/20220509175616.1089346-4-clg@kaod.org
Signed-off-by: Mark Brown

spi: add driver for MTK SPI NAND Flash Interface

2022-04-27T16:22:53+00:00

This driver implements support for the SPI-NAND mode of MTK NAND Flash
Interface as a SPI-MEM controller with pipelined ECC capability.

Signed-off-by: Chuanhong Guo 
Tested-by: Daniel Golle 
Link: https://lore.kernel.org/r/20220424032527.673605-3-gch981213@gmail.com
Signed-off-by: Mark Brown

mtd: spi-nor / spi / MFD: Convert intel-spi to SPI MEM

2022-02-15T12:53:31+00:00

Merge series from Mika Westerberg :

Based on discussion on the patch I sent some time ago here:

  http://lists.infradead.org/pipermail/linux-mtd/2021-June/086867.html

it turns out that the preferred way to deal with the SPI flash controller
drivers is through SPI MEM which is part of Linux SPI subsystem.

This series does that for the intel-spi driver. This also renames the
driver to follow the convention used in the SPI subsystem. The first patch
improves the write protection handling to be slightly more safer. The
following two patches do the conversion itself. Note the Intel SPI flash
controller only allows commands such as read, write and so on and it
internally uses whatever addressing etc. it figured from the SFDP on the
flash device.

base-commit: e783362eb54cd99b2cac8b3a9aeac942e6f6ac07

mtd: spi-nor: intel-spi: Convert to SPI MEM

2022-02-14T12:53:09+00:00

The preferred way to implement SPI-NOR controller drivers is through SPI
subsubsystem utilizing the SPI MEM core functions. This converts the
Intel SPI flash controller driver over the SPI MEM by moving the driver
from SPI-NOR subsystem to SPI subsystem and in one go make it use the
SPI MEM functions. The driver name will be changed from intel-spi to
spi-intel to match the convention used in the SPI subsystem.

Signed-off-by: Mika Westerberg 
Reviewed-by: Andy Shevchenko 
Reviewed-by: Mauro Lima 
Reviewed-by: Boris Brezillon 
Acked-by: Lee Jones 
Acked-by: Pratyush Yadav 
Reviewed-by: Tudor Ambarus 
Link: https://lore.kernel.org/r/20220209122706.42439-3-mika.westerberg@linux.intel.com
Signed-off-by: Mark Brown