linux-stable.git/drivers/soc/tegra/fuse, branch linux-6.2.y Linux kernel stable tree soc/tegra: fuse: Use platform info with SoC revision 2022-11-11T14:00:07+00:00 Kartik kkartik@nvidia.com 2022-11-09T14:20:22+00:00 bebf683ba6829f544011411580bcd620b7581087 Tegra pre-silicon platforms do not have chip revisions. This makes the revision SoC attribute meaningless on these platforms. Instead, populate the revision SoC attribute with a combination of the platform name and the chip revision for silicon platforms, and simply with the platform name on pre-silicon platforms. Signed-off-by: Kartik <kkartik@nvidia.com> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Tegra pre-silicon platforms do not have chip revisions. This makes the
revision SoC attribute meaningless on these platforms.

Instead, populate the revision SoC attribute with a combination of the
platform name and the chip revision for silicon platforms, and simply
with the platform name on pre-silicon platforms.

Signed-off-by: Kartik <kkartik@nvidia.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Add nvmem keepout list 2022-10-24T15:09:55+00:00 Kartik kkartik@nvidia.com 2022-10-07T09:51:07+00:00 cc5b2ad5393ec237c8697bb3989a34c0c3beb2f6 On Tegra186 and later, various FUSE offsets are restricted and cannot be accessed from CCPLEX. Currently nvmem binary interface allows reading such offsets from userspace, which results in RAS errors. Add nvmem keepout lists to avoid any reads to restricted offsets. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
On Tegra186 and later, various FUSE offsets are restricted and cannot be
accessed from CCPLEX. Currently nvmem binary interface allows reading
such offsets from userspace, which results in RAS errors.

Add nvmem keepout lists to avoid any reads to restricted offsets.

Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Use SoC specific nvmem cells 2022-10-24T15:09:06+00:00 Kartik kkartik@nvidia.com 2022-10-07T09:51:06+00:00 bea06d776d8b2caeddc45f4810ac1d8dab09b006 Tegra FUSE block size, availability and offsets can vary from one SoC generation to another. Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Tegra FUSE block size, availability and offsets can vary from one SoC
generation to another.

Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Merge tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers 2022-09-23T16:04:29+00:00 Arnd Bergmann arnd@arndb.de 2022-09-23T16:04:29+00:00 3919d905351f279593dd7ec35a23a417963f44a3 soc/tegra: cbb: Changes for v6.1-rc1 This introduces the CBB driver that is used to provide (a lot of) information about SErrors when things go wrong, instead of the kernel just crashing or hanging. * tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: soc/tegra: cbb: Add support for Tegra241 (Grace) soc/tegra: cbb: Add driver for Tegra234 CBB 2.0 soc/tegra: cbb: Add CBB 1.0 driver for Tegra194 soc/tegra: Set ERD bit to mask inband errors Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com Signed-off-by: Arnd Bergmann <arnd@arndb.de> 
soc/tegra: cbb: Changes for v6.1-rc1

This introduces the CBB driver that is used to provide (a lot of)
information about SErrors when things go wrong, instead of the kernel
just crashing or hanging.

* tag 'tegra-for-6.1-cbb' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  soc/tegra: cbb: Add support for Tegra241 (Grace)
  soc/tegra: cbb: Add driver for Tegra234 CBB 2.0
  soc/tegra: cbb: Add CBB 1.0 driver for Tegra194
  soc/tegra: Set ERD bit to mask inband errors

Link: https://lore.kernel.org/r/20220916101957.1635854-2-thierry.reding@gmail.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
soc/tegra: fuse: Add missing of_node_put() 2022-09-15T10:38:43+00:00 Liang He windhl@126.com 2022-06-15T12:32:32+00:00 0a3c2dbec425b82d9af7aeb5dc9b18da398992a7 In tegra_init_apbmisc(), of_find_matching_node() will return a node pointer with refcount incremented. We should use of_node_put() in each failure path or when it is not used anymore. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
In tegra_init_apbmisc(), of_find_matching_node() will return a node
pointer with refcount incremented. We should use of_node_put() in each
failure path or when it is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Add missing of_node_put() in tegra_init_fuse() 2022-09-15T10:38:43+00:00 Liang He windhl@126.com 2022-06-16T01:46:36+00:00 e941712cccab8a96f03b5d3274159c1ed338efee In this function, of_find_matching_node() will return a node pointer with refcount incremented. We should use of_node_put() when the "np" pointer is not used anymore. Signed-off-by: Liang He <windhl@126.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
In this function, of_find_matching_node() will return a node pointer
with refcount incremented. We should use of_node_put() when the "np"
pointer is not used anymore.

Signed-off-by: Liang He <windhl@126.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: Set ERD bit to mask inband errors 2022-09-15T10:30:11+00:00 Sumit Gupta sumitg@nvidia.com 2022-05-11T20:16:43+00:00 96765cc47546fe6724825600afa8ba170671da61 Add a function to set the ERD (Error Response Disable) bit in the MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error handler driver. ERD bit allows masking of SError due to inband errors which are caused by illegal register accesses through CBB. When the bit is set, interrupt is used for reporting errors and magic code '0xdead2003' is returned. This change is only required for Tegra194 SoC as the config is moved to CBB register space for future SoC's. Also, remove unmapping the apbmisc_base as it's required to get the base address for accessing the misc register. Signed-off-by: Sumit Gupta <sumitg@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add a function to set the ERD (Error Response Disable) bit in the
MISCREG_CCROC_ERR_CONFIG register from the Control Backbone (CBB) error
handler driver.

ERD bit allows masking of SError due to inband errors which are caused
by illegal register accesses through CBB. When the bit is set, interrupt
is used for reporting errors and magic code '0xdead2003' is returned.
This change is only required for Tegra194 SoC as the config is moved to
CBB register space for future SoC's. Also, remove unmapping the
apbmisc_base as it's required to get the base address for accessing the
misc register.

Signed-off-by: Sumit Gupta <sumitg@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Add nvmem cell lookup entries for Tegra194 2022-04-06T12:55:50+00:00 Sagar Kamble skamble@nvidia.com 2022-03-24T12:08:48+00:00 942501661fa65f13bf9b5582e8248e92770b2d93 Add nvmem cell lookup entries for below FUSE cells: - gcplex-config-fuse - pdi0 - pdi1 Also include the device name prefix "gpu-" in the names of the GPU FUSE cells in nvmem_cell_info. Signed-off-by: Sagar Kamble <skamble@nvidia.com> Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Add nvmem cell lookup entries for below FUSE cells:
 - gcplex-config-fuse
 - pdi0
 - pdi1

Also include the device name prefix "gpu-" in the names of the GPU FUSE
cells in nvmem_cell_info.

Signed-off-by: Sagar Kamble <skamble@nvidia.com>
Reviewed-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Explicitly cast to/from __iomem 2022-02-24T16:09:13+00:00 Thierry Reding treding@nvidia.com 2022-02-24T12:27:28+00:00 b631c9c2ae934ce2a563853e8e6a591f7d34b48b sparse is picky about casts between different address spaces. A cast to plain void * needs to be accompanied by a __force modifier and casting back to void __iomem * needs to be explicit to avoid warnings. Reported-by: kernel test robot <lkp@intel.com> Fixes: 88724b78a84c ("soc/tegra: fuse: Use resource-managed helpers") Signed-off-by: Thierry Reding <treding@nvidia.com> Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
sparse is picky about casts between different address spaces. A cast to
plain void * needs to be accompanied by a __force modifier and casting
back to void __iomem * needs to be explicit to avoid warnings.

Reported-by: kernel test robot <lkp@intel.com>
Fixes: 88724b78a84c ("soc/tegra: fuse: Use resource-managed helpers")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
soc/tegra: fuse: Update nvmem cell list 2022-02-24T16:09:13+00:00 kartik kkartik@nvidia.com 2021-12-06T11:52:45+00:00 6f259bf1619bbff6118c1e556044c0cb4020bbb6 Update tegra_fuse_cells with below entries: - gcplex-config-fuse: Configuration bits for GPU, used to enable/disable write protected region used for storing GPU firmware. - pdi0: Unique per chip public identifier. - pdi1: Unique per chip public identifier. Signed-off-by: Prathamesh Shete <pshete@nvidia.com> Signed-off-by: Kartik <kkartik@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com> 
Update tegra_fuse_cells with below entries:

 - gcplex-config-fuse:
     Configuration bits for GPU, used to enable/disable write protected
     region used for storing GPU firmware.
 - pdi0:
     Unique per chip public identifier.
 - pdi1:
     Unique per chip public identifier.

Signed-off-by: Prathamesh Shete <pshete@nvidia.com>
Signed-off-by: Kartik <kkartik@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>