linux-stable.git/drivers/soc/qcom, branch v5.18.3

soc: qcom: llcc: Add MODULE_DEVICE_TABLE()

2022-06-09T08:30:23+00:00

[ Upstream commit 5334a3b12a7233b31788de60d61bfd890059d783 ]

The llcc-qcom driver can be compiled as a module, but lacks
MODULE_DEVICE_TABLE() and will therefore not be loaded automatically.
Fix this.

Fixes: a3134fb09e0b ("drivers: soc: Add LLCC driver")
Signed-off-by: Bjorn Andersson 
Reviewed-by: Sai Prakash Ranjan 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20220408213336.581661-3-bjorn.andersson@linaro.org
Signed-off-by: Sasha Levin

soc: qcom: smsm: Fix missing of_node_put() in smsm_parse_ipc

2022-06-09T08:30:22+00:00

[ Upstream commit aad66a3c78da668f4506356c2fdb70b7a19ecc76 ]

The device_node pointer is returned by of_parse_phandle()  with refcount
incremented. We should use of_node_put() on it when done.

Fixes: c97c4090ff72 ("soc: qcom: smsm: Add driver for Qualcomm SMSM")
Signed-off-by: Miaoqian Lin 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220308073648.24634-1-linmq006@gmail.com
Signed-off-by: Sasha Levin

soc: qcom: smp2p: Fix missing of_node_put() in smp2p_parse_ipc

2022-06-09T08:30:22+00:00

[ Upstream commit 8fd3f18ea31a398ecce4a6d3804433658678b0a3 ]

The device_node pointer is returned by of_parse_phandle()  with refcount
incremented. We should use of_node_put() on it when done.

Fixes: 50e99641413e ("soc: qcom: smp2p: Qualcomm Shared Memory Point to Point")
Signed-off-by: Miaoqian Lin 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220308071942.22942-1-linmq006@gmail.com
Signed-off-by: Sasha Levin

soc: qcom: rpmpd: Add MSM8226 support

2022-02-24T20:12:34+00:00

Add the power domains preset in MSM8226.

Signed-off-by: Luca Weiss 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220220223004.507739-2-luca@z3ntu.xyz

soc: qcom: mdt_loader: Fix split-firmware condition

2022-02-23T19:13:12+00:00

The updated condition checking if a segment can be found in the loaded
firmware blob, or need to be loaded from a separate file, incorrectly
classifies segments that ends at the end of the loaded blob. The result
is that the mdt loader attempts to load the segment from a separate
file.

Correct the conditional to use the loaded segment instead.

Fixes: ea90330fa329 ("soc: qcom: mdt_loader: Extend check for split firmware")
Signed-off-by: Bjorn Andersson 
Reviewed-by: Vinod Koul 
Link: https://lore.kernel.org/r/20220215034819.1209367-1-bjorn.andersson@linaro.org

soc: qcom: llcc: Add configuration data for SM8450 SoC

2022-02-11T00:29:33+00:00

Add LLCC configuration data for SM8450 SoC.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/fec944cb8f2a4a70785903c6bfec629c6f31b6a4.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Update register offsets for newer LLCC HW

2022-02-11T00:29:33+00:00

Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/c655d16d945aef2d7fc8e7c212f3e1c58a84eb95.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Add missing llcc configuration data

2022-02-11T00:29:33+00:00

Add missing llcc configuration data for few chipsets which
were not added during initial post.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/143d11bacaca086406fdd10fc32f91eccd943527.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Add write-cache cacheable support

2022-02-11T00:29:33+00:00

Newer SoCs with LLCC IP version 2.1.0.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/83372c8178f579d055ec58212ce5af5d55abadd4.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Update the logic for version info extraction

2022-02-11T00:29:33+00:00

LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions v2.0.0.0 and later, also upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/a82d7c32348c51fcc2b63e220d91b318bf706c83.1643355594.git.quic_saipraka@quicinc.com