linux-stable.git/drivers/soc/qcom, branch v5.18.2

soc: qcom: rpmpd: Add MSM8226 support

2022-02-24T20:12:34+00:00

Add the power domains preset in MSM8226.

Signed-off-by: Luca Weiss 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/20220220223004.507739-2-luca@z3ntu.xyz

soc: qcom: mdt_loader: Fix split-firmware condition

2022-02-23T19:13:12+00:00

The updated condition checking if a segment can be found in the loaded
firmware blob, or need to be loaded from a separate file, incorrectly
classifies segments that ends at the end of the loaded blob. The result
is that the mdt loader attempts to load the segment from a separate
file.

Correct the conditional to use the loaded segment instead.

Fixes: ea90330fa329 ("soc: qcom: mdt_loader: Extend check for split firmware")
Signed-off-by: Bjorn Andersson 
Reviewed-by: Vinod Koul 
Link: https://lore.kernel.org/r/20220215034819.1209367-1-bjorn.andersson@linaro.org

soc: qcom: llcc: Add configuration data for SM8450 SoC

2022-02-11T00:29:33+00:00

Add LLCC configuration data for SM8450 SoC.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/fec944cb8f2a4a70785903c6bfec629c6f31b6a4.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Update register offsets for newer LLCC HW

2022-02-11T00:29:33+00:00

Newer LLCC HW have different register offsets for several registers,
currently of which LLCC hardware info and status are used to identify
the LLCC version information and other data. So use separate table to
keep track of these register offsets which vary by different LLCC HW
versions and eases any future addition in variations of register offsets
for newer hardware.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/c655d16d945aef2d7fc8e7c212f3e1c58a84eb95.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Add missing llcc configuration data

2022-02-11T00:29:33+00:00

Add missing llcc configuration data for few chipsets which
were not added during initial post.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/143d11bacaca086406fdd10fc32f91eccd943527.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Add write-cache cacheable support

2022-02-11T00:29:33+00:00

Newer SoCs with LLCC IP version 2.1.0.0 and later support write
sub-cache cacheable feature. Use a separate llcc_slice_config member
"write_scid_cacheable_en" to identify this feature and program
LLCC_TRP_SCID_WRSC_CACHEABLE_EN register to enable it.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/83372c8178f579d055ec58212ce5af5d55abadd4.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Update the logic for version info extraction

2022-02-11T00:29:33+00:00

LLCC HW version info is made up of major, branch, minor and echo
version bits each of which are 8bits. Several features in newer
LLCC HW are based on the full version rather than just major or
minor versions such as write-subcache enable which is applicable
for versions v2.0.0.0 and later, also upcoming write-subcache
cacheable for SM8450 SoC which is only present in versions v2.1.0.0
and later, so it makes it easier and cleaner to just directly
compare with the full version than adding additional major/branch/
minor/echo version checks. So remove the earlier major version check
and add full version check for those features.

Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/a82d7c32348c51fcc2b63e220d91b318bf706c83.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: llcc: Add support for 16 ways of allocation

2022-02-11T00:29:33+00:00

Add support for 16 ways of allocation for LLCC HW version 2.1.0
and later.

Signed-off-by: Huang Yiwei 
Signed-off-by: Sai Prakash Ranjan 
Tested-by: Vinod Koul 
Signed-off-by: Bjorn Andersson 
Link: https://lore.kernel.org/r/a7a5f64259c2c02628f03fb59b91e9fa78da2dfb.1643355594.git.quic_saipraka@quicinc.com

soc: qcom: socinfo: Add some more PMICs and SoCs

2022-02-10T23:53:00+00:00

Add SM8350, SC8280XP, SA8540P and one more SM8450 and various PMICs
found on boards on these platforms to the socinfo driver.

Signed-off-by: Bjorn Andersson 
Tested-by: Vinod Koul 
Reviewed-by: Vinod Koul 
Link: https://lore.kernel.org/r/20220210051043.748275-1-bjorn.andersson@linaro.org

soc: qcom: mdt_loader: Extract PAS operations

2022-02-04T03:54:48+00:00

Rather than passing a boolean to indicate if the PAS operations should
be performed from within __mdt_load(), extract them to their own helper
function.

This will allow clients to invoke this directly, with some
qcom_scm_pas_metadata context that they later needs to release, without
further having to complicate the prototype of qcom_mdt_load().

Signed-off-by: Bjorn Andersson 
Reviewed-by: Dmitry Baryshkov 
Link: https://lore.kernel.org/r/20220128025513.97188-9-bjorn.andersson@linaro.org