linux-stable.git/drivers/soc/mediatek, branch linux-5.17.y

soc: mediatek: pm-domains: Add wakeup capacity support in power domain

2022-04-08T11:57:49+00:00

[ Upstream commit ac0ca395543af061f7ad77afcda0afb323d82468 ]

Due to some power domain needs to keep on for wakeup in system suspend,
so add GENPD_FLAG_ACTIVE_WAKEUP support in Mediatek power domain driver.

Fixes: 59b644b01cf4 ("soc: mediatek: Add MediaTek SCPSYS power domains")
Signed-off-by: Chun-Jie Chen 
Reviewed-by: Chen-Yu Tsai 
Reviewed-by: AngeloGioacchino Del Regno 
Link: https://lore.kernel.org/r/20220130012104.5292-3-chun-jie.chen@mediatek.com
Signed-off-by: Matthias Brugger 
Signed-off-by: Sasha Levin

soc: mediatek: mt8192-mmsys: Fix dither to dsi0 path's input sel

2022-03-01T07:36:59+00:00

In commit d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table"),
the mmsys routing table for mt8192 was introduced but the input selector
for DITHER->DSI0 has no value assigned to it.

This means that we are clearing bit 0 instead of setting it, blocking
communication between these two blocks; due to that, any display that
is connected to DSI0 will not work, as no data will go through.
The effect of that issue is that, during bootup, the DRM will block for
some time, while atomically waiting for a vblank that never happens;
later, the situation doesn't get better, leaving the display in a
non-functional state.

To fix this issue, fix the route entry in the table by assigning the
dither input selector to MT8192_DISP_DSI0_SEL_IN.

Fixes: d687e056a18f ("soc: mediatek: mmsys: Add mt8192 mmsys routing table")
Signed-off-by: AngeloGioacchino Del Regno 
Tested-by: Alyssa Rosenzweig 
Reviewed-by: Nícolas F. R. A. Prado 
Link: https://lore.kernel.org/r/20220128142056.359900-1-angelogioacchino.delregno@collabora.com
Signed-off-by: Matthias Brugger

ASoC: Revert "ASoC: mediatek: Check for error clk pointer"

2022-02-08T13:37:39+00:00

This reverts commit 9de2b9286a6d ("ASoC: mediatek: Check for error clk
pointer").

With this patch in the tree, Chromebooks running the affected hardware
no longer boot. Bisect points to this patch, and reverting it fixes
the problem.

An analysis of the code with this patch applied shows:

        ret = init_clks(pdev, clk);
        if (ret)
                return ERR_PTR(ret);
...
                for (j = 0; j < MAX_CLKS && data->clk_id[j]; j++) {
                        struct clk *c = clk[data->clk_id[j]];

                        if (IS_ERR(c)) {
                                dev_err(&pdev->dev, "%s: clk unavailable\n",
                                        data->name);
                                return ERR_CAST(c);
                        }

                        scpd->clk[j] = c;
                }

Not all clocks in the clk_names array have to be present. Only the clocks
in the data->clk_id array are actually needed. The code already checks if
the required clocks are available and bails out if not. The assumption that
all clocks have to be present is wrong, and commit 9de2b9286a6d ("ASoC:
mediatek: Check for error clk pointer") needs to be reverted.

Cc: Jiasheng Jiang 
Cc: Mark Brown 
Cc: James Liao 
Cc: Kevin Hilman 
Cc: Matthias Brugger 
Reported-by: Frank Wunderlich 
Reported-by: Daniel Golle 
Fixes: 9de2b9286a6d ("ASoC: mediatek: Check for error clk pointer")
Signed-off-by: Guenter Roeck 
Link: https://lore.kernel.org/r/20220207160923.3911501-1-linux@roeck-us.net
Signed-off-by: Mark Brown

ASoC: mediatek: Check for error clk pointer

2021-12-24T14:06:57+00:00

Yes, you are right and now the return code depending on the
init_clks().

Fixes: 6078c651947a ("soc: mediatek: Refine scpsys to support multiple platform")
Signed-off-by: Jiasheng Jiang 
Link: https://lore.kernel.org/r/20211222015157.1025853-1-jiasheng@iscas.ac.cn
Signed-off-by: Mark Brown

soc: mediatek: mmsys: Add reset controller support

2021-10-08T13:15:26+00:00

Among other features the mmsys driver should implement a reset
controller to be able to reset different bits from their space.

Cc: Jitao Shi 
Suggested-by: Chun-Kuang Hu 
Signed-off-by: Enric Balletbo i Serra 
Reviewed-by: Philipp Zabel 
Link: https://lore.kernel.org/r/20210930103105.v4.6.I15e2419141a69b2e5c7e700c34d92a69df47e04d@changeid
Signed-off-by: Matthias Brugger

soc: mediatek: add mtk mutex support for MT8192

2021-10-08T11:25:43+00:00

Add mtk mutex support for MT8192 SoC.

Signed-off-by: Yongqiang Niu 
Signed-off-by: Hsin-Yi Wang 
Reviewed-by: CK Hu 
Link: https://lore.kernel.org/r/20210930155222.5861-5-yongqiang.niu@mediatek.com
Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: Add mt8192 mmsys routing table

2021-09-13T08:52:13+00:00

mt8192 has different routing registers than mt8183

Signed-off-by: Yongqiang Niu 
Link: https://lore.kernel.org/r/1627894773-23872-3-git-send-email-yongqiang.niu@mediatek.com
[mb: take mask into account]
Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: Fix missing UFOE component in mt8173 table routing

2021-08-06T14:43:23+00:00

The UFOE (data compression engine) component needs to be enabled to have
the imgtec gpu driver working. If we don't enable it we see a black screen.
Looks like when we switched to use and array for setting the routing
registers in commit 440147639ac7 ("soc: mediatek: mmsys: Use an array for
setting the routing registers") we missed to add this component in the new
routing table, it was present before that commit, so fix it by adding
this component in the mt8173 routing table.

Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Enric Balletbo i Serra 
Tested-by: Eizan Miyamoto 
Cc: 
Link: https://lore.kernel.org/r/20210625062448.3462177-1-enric.balletbo@collabora.com
[mb: taking into account mask value]
Signed-off-by: Matthias Brugger

soc: mediatek: mmsys: add MT8365 support

2021-08-06T14:43:23+00:00

Add DSI mmsys connections for the MT8365 SoC.

Signed-off-by: Fabien Parent 
Link: https://lore.kernel.org/r/20210519161847.3747352-3-fparent@baylibre.com
[mb: take the mask field into account]
Signed-off-by: Matthias Brugger

soc: mmsys: mediatek: add mask to mmsys routes

2021-08-04T17:05:46+00:00

SOUT has many bits and need to be cleared before set new value.
Write only could do the clear, but for MOUT, it clears bits that
should not be cleared. So use a mask to reset only the needed bits.

this fixes HDMI issues on MT7623/BPI-R2 since 5.13

Fixes: 440147639ac7 ("soc: mediatek: mmsys: Use an array for setting the routing registers")
Signed-off-by: Frank Wunderlich 
Signed-off-by: CK Hu 
Reviewed-by: Chun-Kuang Hu 
Reviewed-by: Hsin-Yi Wang 
Link: https://lore.kernel.org/r/20210729070549.5514-1-linux@fw-web.de
Signed-off-by: Matthias Brugger