linux-stable.git/drivers/soc/imx, branch v5.2.2

treewide: Add SPDX license identifier - Makefile/Kconfig

2019-05-21T08:50:46+00:00

Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner 
Signed-off-by: Greg Kroah-Hartman

Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2019-05-16T16:19:14+00:00

Pull ARM SoC-related driver updates from Olof Johansson:
 "Various driver updates for platforms and a couple of the small driver
  subsystems we merge through our tree:

  Among the larger pieces:

   - Power management improvements for TI am335x and am437x (RTC
     suspend/wake)

   - Misc new additions for Amlogic (socinfo updates)

   - ZynqMP FPGA manager

   - Nvidia improvements for reset/powergate handling

   - PMIC wrapper for Mediatek MT8516

   - Misc fixes/improvements for ARM SCMI, TEE, NXP i.MX SCU drivers"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
  soc: aspeed: fix Kconfig
  soc: add aspeed folder and misc drivers
  spi: zynqmp: Fix build break
  soc: imx: Add generic i.MX8 SoC driver
  MAINTAINERS: Update email for Qualcomm SoC maintainer
  memory: tegra: Fix a typos for "fdcdwr2" mc client
  Revert "ARM: tegra: Restore memory arbitration on resume from LP1 on Tegra30+"
  memory: tegra: Replace readl-writel with mc_readl-mc_writel
  memory: tegra: Fix integer overflow on tick value calculation
  memory: tegra: Fix missed registers values latching
  ARM: tegra: cpuidle: Handle tick broadcasting within cpuidle core on Tegra20/30
  optee: allow to work without static shared memory
  soc/tegra: pmc: Move powergate initialisation to probe
  soc/tegra: pmc: Remove reset sysfs entries on error
  soc/tegra: pmc: Fix reset sources and levels
  soc: amlogic: meson-gx-pwrc-vpu: Add support for G12A
  soc: amlogic: meson-gx-pwrc-vpu: Fix power on/off register bitmask
  fpga manager: Adding FPGA Manager support for Xilinx zynqmp
  dt-bindings: fpga: Add bindings for ZynqMP fpga driver
  firmware: xilinx: Add fpga API's
  ...

soc: imx: gpc: Use GENPD_FLAG_RPM_ALWAYS_ON for ERR009619

2019-05-13T08:51:31+00:00

This allows PU domain to be turned off in suspend and save power.

Signed-off-by: Leonard Crestez 
Reviewed-by: Ulf Hansson 
Signed-off-by: Rafael J. Wysocki

soc: imx: Add generic i.MX8 SoC driver

2019-04-20T13:26:36+00:00

Add generic i.MX8 SoC driver along with the i.MX8MQ SoC specific code.
For now, only i.MX8MQ revision B1 is supported. For any other, i.MX8MQ
revision it will print 'unknown'.

Signed-off-by: Abel Vesa 
Reviewed-by: Leonard Crestez 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: use devm_platform_ioremap_resource() to simplify code

2019-04-11T07:16:44+00:00

Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.

Signed-off-by: Anson Huang 
Reviewed-by: Mukesh Ojha 
Signed-off-by: Shawn Guo

soc: imx: gpc: use devm_platform_ioremap_resource() to simplify code

2019-04-11T07:16:39+00:00

Use the new helper devm_platform_ioremap_resource() which wraps the
platform_get_resource() and devm_ioremap_resource() together, to
simplify the code.

Signed-off-by: Anson Huang 
Reviewed-by: Mukesh Ojha 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: Make use of regmap_read_poll_timeout()

2019-03-19T08:47:09+00:00

Replace explicit polling loop with a call to
regmap_read_poll_timeout() to avoid code repetition. Also fix
misspelled "failed" while at it.

Signed-off-by: Andrey Smirnov 
Cc: Lucas Stach 
Cc: Chris Healy 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Reviewed-by: Lucas Stach 
Signed-off-by: Shawn Guo

soc: imx: Break dependency on SOC_IMX8MQ for GPCv2

2019-01-14T01:42:22+00:00

Since this is going to be used on more SoCs than just i.MX8MQ, make
the dependency here more generic by using ARCH_MXC instead.
Also remove the SOC_IMX7D since it is also included by the ARCH_MXC.

Signed-off-by: Abel Vesa 
Reviewed-by: Dong Aisheng 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: handle reset clocks

2019-01-11T07:12:59+00:00

Some power domains handled by the GPCv2 driver need to enable the clocks
for devies inside the domain, so that the reset propagation and proper
power-up sequencing happens. Handle them in the same way as on GPCv1.

Signed-off-by: Lucas Stach 
Acked-by: Rob Herring 
Signed-off-by: Shawn Guo

soc: imx: gpcv2: handle additional power-down bits in handshake register

2019-01-11T07:12:38+00:00

Some of the i.MX8MQ domains have an additional control bit in the PU
handshake (HSK) register. Documentation about this bit is a bit sparse
at the moment, but it seems that it controls a power-down request to
the AMBA domain bridge (ADB-400) attached to those domains.

As the documentation doesn't desribe the usage of this bit yet, handle
it in the same way as done in the ATF implementation.

Signed-off-by: Lucas Stach 
Signed-off-by: Shawn Guo