linux-stable.git/drivers/reset/Kconfig, branch v5.3 Linux kernel stable tree Merge tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux into arm/drivers 2019-07-04T14:05:23+00:00 Olof Johansson olof@lixom.net 2019-07-04T14:05:21+00:00 8c0993621c3e5fa52e5425ef2a0f67a0cde07092 Reset controller changes for v5.3 This tag adds support for the Bitmain BM1880 reset controller to the reset-simple driver and fixes a spelling mistake in the i.MX7 reset controller binding document. * tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux: dt-bindings: reset: imx7: Fix the spelling of 'indices' reset: Add reset controller support for BM1880 SoC dt-bindings: reset: Add devicetree binding for BM1880 reset controller Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de Signed-off-by: Olof Johansson <olof@lixom.net> 
Reset controller changes for v5.3

This tag adds support for the Bitmain BM1880 reset controller to the
reset-simple driver and fixes a spelling mistake in the i.MX7 reset
controller binding document.

* tag 'reset-for-v5.3' of git://git.pengutronix.de/git/pza/linux:
  dt-bindings: reset: imx7: Fix the spelling of 'indices'
  reset: Add reset controller support for BM1880 SoC
  dt-bindings: reset: Add devicetree binding for BM1880 reset controller

Link: https://lore.kernel.org/r/1562236632.6641.14.camel@pengutronix.de
Signed-off-by: Olof Johansson <olof@lixom.net>
reset: Add reset controller support for BM1880 SoC 2019-05-24T14:08:14+00:00 Manivannan Sadhasivam manivannan.sadhasivam@linaro.org 2019-05-10T18:45:24+00:00 64c47b624f64cf8594cc5dc3330e161848eaa15b Add reset controller support for Bitmain BM1880 SoC reusing the reset-simple driver. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add reset controller support for Bitmain BM1880 SoC reusing the
reset-simple driver.

Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
treewide: Add SPDX license identifier - Makefile/Kconfig 2019-05-21T08:50:46+00:00 Thomas Gleixner tglx@linutronix.de 2019-05-19T12:07:45+00:00 ec8f24b7faaf3d4799a7c3f4c1b87f6b02778ad1 Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> 
Add SPDX license identifiers to all Make/Kconfig files which:

 - Have no license information of any form

These files fall under the project license, GPL v2 only. The resulting SPDX
license identifier is:

  GPL-2.0-only

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
reset: imx7: Add support for i.MX8MQ IP block variant 2019-01-28T10:16:04+00:00 Andrey Smirnov andrew.smirnov@gmail.com 2019-01-22T02:10:43+00:00 c979dbf59987f4114fdbd491c8ad254343a430fd Add bits and pieces needed to support IP block variant found on i.MX8MQ SoCs. Cc: p.zabel@pengutronix.de Cc: Fabio Estevam <fabio.estevam@nxp.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: Rob Herring <robh@kernel.org> Cc: devicetree@vger.kernel.org Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> [p.zabel@pengutronix.de: fixed whitespace alignment] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add bits and pieces needed to support IP block variant found on
i.MX8MQ SoCs.

Cc: p.zabel@pengutronix.de
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: cphealy@gmail.com
Cc: l.stach@pengutronix.de
Cc: Leonard Crestez <leonard.crestez@nxp.com>
Cc: "A.s. Dong" <aisheng.dong@nxp.com>
Cc: Richard Zhu <hongxing.zhu@nxp.com>
Cc: Rob Herring <robh@kernel.org>
Cc: devicetree@vger.kernel.org
Cc: linux-imx@nxp.com
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com>
[p.zabel@pengutronix.de: fixed whitespace alignment]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: Add Broadcom STB SW_INIT reset controller driver 2019-01-28T10:16:04+00:00 Florian Fainelli f.fainelli@gmail.com 2019-01-23T22:54:36+00:00 77750bc089e4508ff62f036e6e6626cf8d7384cb Add support for resetting blocks through the Linux reset controller subsystem when reset lines are provided through a SW_INIT-style reset controller on Broadcom STB SoCs. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add support for resetting blocks through the Linux reset controller
subsystem when reset lines are provided through a SW_INIT-style reset
controller on Broadcom STB SoCs.

Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: uniphier-usb3: Rename to reset-uniphier-glue 2019-01-07T15:38:51+00:00 Kunihiko Hayashi hayashi.kunihiko@socionext.com 2018-11-09T01:42:05+00:00 3eb8f765f5aeca6e4195246f41e534025f69eee8 This driver works for controlling the reset lines including USB3 glue layer, however, this can be applied to other glue layers. Now this patch renames the driver from "reset-uniphier-usb3" to "reset-uniphier-glue". At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to CONFIG_RESET_UNIPHIER_GLUE. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
This driver works for controlling the reset lines including USB3
glue layer, however, this can be applied to other glue layers.
Now this patch renames the driver from "reset-uniphier-usb3" to
"reset-uniphier-glue".

At the same time, this changes CONFIG_RESET_UNIPHIER_USB3 to
CONFIG_RESET_UNIPHIER_GLUE.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: socfpga: add an early reset driver for SoCFPGA 2019-01-07T15:38:50+00:00 Dinh Nguyen dinguyen@kernel.org 2018-11-13T18:50:48+00:00 b3ca9888f35fa6919569cf27c929dc0ac49e9716 Create a separate reset driver that uses the reset operations in reset-simple. The reset driver for the SoCFPGA platform needs to register early in order to be able bring online timers that needed early in the kernel bootup. We do not need this early reset driver for Stratix10, because on arm64, Linux does not need the timers are that in reset. Linux is able to run just fine with the internal armv8 timer. Thus, we use a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform. The Stratix10 platform will continue to use the reset-simple platform driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use the early reset driver. Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> [p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple] Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Create a separate reset driver that uses the reset operations in
reset-simple. The reset driver for the SoCFPGA platform needs to
register early in order to be able bring online timers that needed
early in the kernel bootup.

We do not need this early reset driver for Stratix10, because on
arm64, Linux does not need the timers are that in reset. Linux is
able to run just fine with the internal armv8 timer. Thus, we use
a new binding "altr,stratix10-rst-mgr" for the Stratix10 platform.
The Stratix10 platform will continue to use the reset-simple platform
driver, while the 32-bit platforms(Cyclone5/Arria5/Arria10) will use
the early reset driver.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
[p.zabel@pengutronix.de: fixed socfpga of_device_id in reset-simple]
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: qcom: PDC Global (Power Domain Controller) reset controller 2018-10-05T08:33:44+00:00 Sibi Sankar sibis@codeaurora.org 2018-08-29T19:12:11+00:00 eea2926b0a390969828e49ea96c45a2b1f007030 Add reset controller for SDM845 SoCs to control reset signals provided by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add reset controller for SDM845 SoCs to control reset signals provided
by PDC Global for Modem, Compute, Display, GPU, Debug, AOP, Sensors,
Audio, SP and APPS

Signed-off-by: Sibi Sankar <sibis@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: meson: add meson audio arb driver 2018-07-20T16:17:31+00:00 Jerome Brunet jbrunet@baylibre.com 2018-07-20T15:26:33+00:00 d903779b58be442f3afd2c51c46c7cf19c97684e The Amlogic Audio ARB is a simple device which enables or disables the access of Audio FIFOs to DDR on AXG based SoC. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
The Amlogic Audio ARB is a simple device which enables or
disables the access of Audio FIFOs to DDR on AXG based SoC.

Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
reset: uniphier: add USB3 core reset control 2018-07-16T10:15:55+00:00 Kunihiko Hayashi hayashi.kunihiko@socionext.com 2018-07-10T01:14:17+00:00 499fef09a3237497906084da3eede0185fc9abb8 Add a reset line to enable USB3 core implemented in UniPhier SoCs. This reuses only the reset operations in reset-simple, because the reset-simple doesn't handle any SoC-dependent clocks and resets. This reset line is included in the USB3 glue layer, and it's necessary to enable clocks and deassert resets of the layer before using this reset line. Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> 
Add a reset line to enable USB3 core implemented in UniPhier SoCs.

This reuses only the reset operations in reset-simple, because
the reset-simple doesn't handle any SoC-dependent clocks and resets.
This reset line is included in the USB3 glue layer, and it's necessary
to enable clocks and deassert resets of the layer before using this
reset line.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>