linux-stable.git/drivers/pinctrl, branch v7.2.6

pinctrl: rockchip: Decode drive strength in the get function

2026-09-14T11:40:37+00:00

[ Upstream commit 8aa25c6e8893ed911b0cad37a5562fda9bc98438 ]

The decoding of the 2-bit and 8-bit level drive-strength values sits in
rockchip_set_drive_perpin(), where it is unreachable: the SoCs whose
banks declare these drive types (RK3506 and RV1103B) take the early
ctrl->type branch in the set path, and the read-and-decode logic in a
set function has no purpose. Meanwhile rockchip_get_drive_perpin()
lacks the decoding, so pin_config_get() and the debugfs output report
-EINVAL for these SoCs.

Move the two cases to rockchip_get_drive_perpin(), where they belong.

Fixes: dbd2317d7b9f ("pinctrl: rockchip: Add rk3506 pinctrl support")
Signed-off-by: Simon Glass 
Reviewed-by: Heiko Stuebner 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: fix PINCTRL_GENERIC_MUX not always being selectable

2026-09-14T11:40:32+00:00

[ Upstream commit 465f276bb928093685c2a2b98bf0a7ccc4283b8d ]

CONFIG_MULTIPLEXER can only be enabled indirectly. If it's not already
enabled, then CONFIG_PINCTRL_GENERIC_MUX cannot be selected at all in
menuconfig. That's because it depends on MULTIPLEXER.

Follow similar consumers of the multiplexer core and select MULTIPLEXER
instead. This way the driver will be visible in menuconfig as long as
PINCTRL is selected.

Fixes: 34acc5a8adfb ("pinctrl: add generic board-level pinctrl driver using mux framework")
Signed-off-by: Alvin Šipraga 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: fix edge-triggered interrupts handling

2026-09-14T11:40:31+00:00

[ Upstream commit 3de4686cdf0ccf6d78ca96ccaea621cbcf69fc3a ]

Edge-triggered interrupts are handled incorrectly because of
 * no irq_ack() handler was defined,
 * no handle_level_irq() handler was used,

This patch probably fixes an issue

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Acked-by: Lorenzo Bianconi 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: fix IRQ mask/unmask code

2026-09-14T11:40:31+00:00

[ Upstream commit 20b996280640f492ebdd41c2d2c991801df75e61 ]

When using IRQCHIP_IMMUTABLE, airoha_irq_unmask() must manually call
gpiochip_enable_irq() and airoha_irq_mask() must call
gpiochip_disable_irq(). Without these calls, gpiolib never sets the
GPIOD_FLAG_IRQ_IS_ENABLED bit. Because this bit is missing,
gpiod_direction_output() will not realize the pin is actively used
as an interrupt.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Acked-by: Lorenzo Bianconi 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: add missed IRQ resource helpers

2026-09-14T11:40:31+00:00

[ Upstream commit a02fa031b9520e46e98bff17e12b472eba770670 ]

Without hooking .irq_request_resources, gpiolib cannot set
GPIOD_FLAG_USED_AS_IRQ. This breaks pin direction locking and can allow
userspace or another driver to reconfigure an active IRQ pin as an output

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Acked-by: Lorenzo Bianconi 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: fix getting gpiochip/pinctrl pointers in the IRQ handling code

2026-09-14T11:40:31+00:00

[ Upstream commit b8dd30554847bde27e8a4584dd447c1c3ac585ce ]

airoha_irq_unmask(), airoha_irq_mask(), airoha_irq_type() functions
impements brain damaged logic to retrieve gpiochip and pinctrl pointers.

Details:

    gpiochip = irq_data_get_irq_chip_data(data);

will initialize gpiochip variable with data->chip_data value. This value
initialized inside gpiochip_irq_map() function

    static int gpiochip_irq_map(struct irq_domain *d, unsigned int irq,
			        irq_hw_number_t hwirq)
    {
	struct gpio_chip *gc = d->host_data;
        ...
	irq_set_chip_data(irq, gc);
	...
    }

Thus gpiochip variable of 'struct airoha_pinctrl_gpiochip *' type will be
initialized with a pointer to a variable of 'struct gpio_chip' type.

Luckily, gpio_chip is the first element of airoha_pinctrl_gpiochip, so
gpiochip pointer will get a correct value.

This patch implements correct logic of getting gpiochip and pinctrl
pointers.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: add missed get_direction() function for gpio_chip

2026-09-14T11:40:31+00:00

[ Upstream commit d6392502a9e6b11c3a93eb4c987672a8c638d749 ]

This patch adds missed get_direction() function for gpio_chip.
Also it reimplements pinconf's get_direction() function using
newly defined function.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: an7583: fix spi group pins

2026-09-14T11:40:31+00:00

[ Upstream commit ccc41d25590645096bdbf420b43e7c22627b3f59 ]

pcm pins were used insted of spi pins. This patch fixes an issue.

Thanks to Daniel Schwierzeck for noticing it.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: an7583: fix muxing of non-gpio default pins

2026-09-14T11:40:31+00:00

[ Upstream commit aaa41d8010c04635e035a9d334885b07edc8af21 ]

Current an7583 pinmux implementation have following issues:
 * pins 51 and 52 can't be set as pcie_reset, current pcie_reset code
   will sets pins to gpio mode instead.
 * there is no proper way to set pins 41--54 to gpio mode.
 * pins 41--53 can't be actually set as pwm pins. These pins must be
   muxed to gpio mode as well.

This patch fixes above issues.

Fixes: 3ffeb17a9a27 ("pinctrl: airoha: add support for Airoha AN7583 PINs")
Signed-off-by: Mikhail Kshevetskiy 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: airoha: an7581: fix mux/conf of pcie_reset pins

2026-09-14T11:40:31+00:00

[ Upstream commit 739bc85aed14b739dca5b7aff4241b778af80220 ]

In the an7581 case
 * gpio47 and pcie_reset0 shares pin 60,
 * gpio48 and pcie_reset1 shares pin 61,
 * gpio49 and pcie_reset2 shares pin 62.
but current driver treat them as pins 61--63. This is wrong.

Also current an7581 pinmux implementation have following issues:
 * current pcie_reset pin function actually sets corresponding
   pins as gpios.
 * there is no proper way to set pcie_reset pins as gpios.
 * there is no way to set pcie_reset pins as pwm.

This patch fixes above issues.

WARNING:
There is a contradiction in the Airoha documentation. AN7581 programming
guide claims:
 - gpio44 and pcie_reset0 shares the same pin
 - gpio45 and pcie_reset1 shares the same pin
 - gpio46 and pcie_reset2 shares the same pin
While AN7581 datasheet claims:
 - gpio47 and pcie_reset0 shares the same pin
 - gpio48 and pcie_reset1 shares the same pin
 - gpio49 and pcie_reset2 shares the same pin
The datasheet should be considered as a more reliable source.
Thanks to Benjamin Larsson for clarification.

Fixes: 1c8ace2d0725 ("pinctrl: airoha: Add support for EN7581 SoC")
Signed-off-by: Mikhail Kshevetskiy 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin