linux-stable.git/drivers/pinctrl, branch v4.6.7

pinctrl: imx: Do not treat a PIN without MUX register as an error

2016-08-10T10:54:46+00:00

commit ba562d5e54fd3136bfea0457add3675850247774 upstream.

Some PINs do not have a MUX register, it is not an error.
It is necessary to allow the continuation of the PINs configuration,
otherwise the whole PIN-group will be configured incorrectly.

Signed-off-by: Alexander Shiyan 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: single: Fix missing flush of posted write for a wakeirq

2016-08-10T10:54:45+00:00

commit 0ac3c0a4025f41748a083bdd4970cb3ede802b15 upstream.

With many repeated suspend resume cycles, the pin specific wakeirq
may not always work on omaps. This is because the write to enable the
pin interrupt may not have reached the device over the interconnect
before suspend happens.

Let's fix the issue with a flush of posted write with a readback.

Reported-by: Nishanth Menon 
Signed-off-by: Tony Lindgren 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: mediatek: fix dual-edge code defect

2016-06-24T17:22:03+00:00

commit 5edf673d07fdcb6498be24914f3f38f8d8843199 upstream.

When a dual-edge irq is triggered, an incorrect irq will be reported on
condition that the external signal is not stable and this incorrect irq
has been registered.
Correct the register offset.

Signed-off-by: Hongkun Cao 
Reviewed-by: Matthias Brugger 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: exynos5440: Use off-stack memory for pinctrl_gpio_range

2016-06-08T01:23:38+00:00

commit 71324fdc72ef0163e57631aa814a9a81e9e4770b upstream.

The range is registered into a linked list which can be referenced
throughout the lifetime of the driver. Ensure the range's memory is useful
for the same lifetime by adding it to the driver's private data structure.

The bug was introduced in the driver's initial commit, which was present in
v3.10.

Fixes: f0b9a7e521fa ("pinctrl: exynos5440: add pinctrl driver for Samsung EXYNOS5440 SoC")
Signed-off-by: Andrew Jeffery 
Acked-by: Tomasz Figa 
Reviewed-by: Krzysztof Kozlowski 
Signed-off-by: Linus Walleij 
Signed-off-by: Greg Kroah-Hartman

pinctrl: at91-pio4: fix pull-up/down logic

2016-04-29T09:16:19+00:00

The default configuration of a pin is often with a value in the
pull-up/down field at chip reset. So, even if the internal logic of the
controller prevents writing a configuration with pull-up and pull-down at
the same time, we must ensure explicitly this condition before writing the
register.

This was leading to a pull-down condition not taken into account for
instance.

Signed-off-by: Ludovic Desroches 
Fixes: 776180848b57 ("pinctrl: introduce driver for Atmel PIO4 controller")
Cc: stable@vger.kernel.org #v4.4 and later
Acked-by: Alexandre Belloni 
Acked-by: Nicolas Ferre 
Signed-off-by: Linus Walleij

pinctrl: single: Fix pcs_parse_bits_in_pinctrl_entry to use __ffs than ffs

2016-04-15T09:26:55+00:00

pcs_parse_bits_in_pinctrl_entry uses ffs which gives bit indices
ranging from 1 to MAX. This leads to a corner case where we try to request
the pin number = MAX and fails.

bit_pos value is being calculted using ffs. pin_num_from_lsb uses
bit_pos value. pins array is populated with:

pin + pin_num_from_lsb.

The above is 1 more than usual bit indices as bit_pos uses ffs to compute
first set bit. Hence the last of the pins array is populated with the MAX
value and not MAX - 1 which causes error when we call pin_request.

mask_pos is rightly calculated as ((pcs->fmask) << (bit_pos - 1))
Consequently val_pos and submask are correct.

Hence use __ffs which gives (ffs(x) - 1) as the first bit set.

fixes: 4e7e8017a8 ("pinctrl: pinctrl-single: enhance to configure multiple pins of different modules")
Signed-off-by: Keerthy 
Acked-by: Tony Lindgren 
Signed-off-by: Linus Walleij

pinctrl: mediatek: correct debounce time unit in mtk_gpio_set_debounce

2016-04-15T08:28:04+00:00

The debounce time unit for gpio_chip.set_debounce is us but
mtk_gpio_set_debounce regard it as ms.
Fix this by correct debounce time array dbnc_arr so it can find correct
debounce setting. Debounce time for first debounce setting is 500us,
correct this as well.

While I'm at it, also change the debounce time array name to
"debounce_time" for readability.

Cc: stable@vger.kernel.org
Signed-off-by: Yingjoe Chen 
Reviewed-by: Daniel Kurtz 
Acked-by: Hongzhou Yang 
Signed-off-by: Linus Walleij

pinctrl: imx: Kconfig: PINCTRL_IMX select REGMAP

2016-04-14T12:19:00+00:00

Regmap functionality has been integrated into pinctrl-imx.c with commit
8626ada8 which might trigger build failures when regmap is not selected
otherwise. Hence, make Kconfig aware about this new dependency.

Signed-off-by: Alexander Kurz 
Acked-by: Philipp Zabel 
Acked-by: Shawn Guo 
Signed-off-by: Linus Walleij

Revert "Revert "pinctrl: lantiq: Implement gpio_chip.to_irq""

2016-04-01T13:21:27+00:00

This reverts commit 446f59acb70b70a425ea4105277a71eb615327cd.

pinctrl: qcom: ipq4019: fix register offsets

2016-03-31T09:56:13+00:00

For this SoC the register offsets changed from previous versions to be
separated by a larger amount.

Signed-off-by: Matthew McClintock 
Acked-by: Björn Andersson 
Signed-off-by: Linus Walleij