linux-stable.git/drivers/pinctrl, branch v4.1.45

pinctrl: samsung: Remove bogus irq_[un]mask from resource management

2017-09-10T20:36:13+00:00

[ Upstream commit 3fa53ec2ed885b0aec3f0472e3b4a8a6f1cd748c ]

The irq chip callbacks irq_request/release_resources() have absolutely no
business with masking and unmasking the irq.

The core code unmasks the interrupt after complete setup and masks it
before invoking irq_release_resources().

The unmask is actually harmful as it happens before the interrupt is
completely initialized in __setup_irq().

Remove it.

Fixes: f6a8249f9e55 ("pinctrl: exynos: Lock GPIOs as interrupts when used as EINTs")
Signed-off-by: Thomas Gleixner 
Cc: Krzysztof Kozlowski 
Cc: Sylwester Nawrocki 
Cc: Linus Walleij 
Cc: Kukjin Kim 
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-samsung-soc@vger.kernel.org
Cc: linux-gpio@vger.kernel.org
Acked-by: Tomasz Figa 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: sunxi: add a missing function of A10/A20 pinctrl driver

2017-09-10T20:36:13+00:00

[ Upstream commit d81ece747d8727bb8b1cfc9a20dbe62f09a4e35a ]

The PH16 pin has a function with mux id 0x5, which is the DET pin of the
"sim" (smart card reader) IP block.

This function is missing in old versions of A10/A20 SoCs' datasheets and
user manuals, so it's also missing in the old drivers. The newest A10
Datasheet V1.70 and A20 Datasheet V1.41 contain this pin function, and
it's discovered during implementing R40 pinctrl driver.

Add it to the driver. As we now merged A20 pinctrl driver to the A10
one, we need to only fix the A10 driver now.

Fixes: f2821b1ca3a2 ("pinctrl: sunxi: Move Allwinner A10 pinctrl
driver to a driver of its own")

Signed-off-by: Icenowy Zheng 
Reviewed-by: Chen-Yu Tsai 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: sh-pfc: Update info pointer after SoC-specific init

2017-07-31T17:37:53+00:00

[ Upstream commit 3091ae775fae17084013021d01513bc1ad274e6a ]

Update the sh_pfc_soc_info pointer after calling the SoC-specific
initialization function, as it may have been updated to e.g. handle
different SoC revisions.  This makes sure the correct subdriver name is
printed later.

Fixes: 0c151062f32c9db8 ("sh-pfc: Add support for SoC-specific initialization")
Signed-off-by: Geert Uytterhoeven 
Signed-off-by: Sasha Levin

pinctrl: mxs: atomically switch mux and drive strength config

2017-07-31T17:37:53+00:00

[ Upstream commit da6c2addf66d7ff7d0b090d6267d4292f951e4e6 ]

To set the mux mode of a pin two bits must be set. Up to now this is
implemented using the following idiom:

	writel(mask, reg + CLR);
	writel(value, reg + SET);

. This however results in the mux mode being 0 between the two writes.

On my machine there is an IC's reset pin connected to LCD_D20. The
bootloader configures this pin as GPIO output-high (i.e. not holding the
IC in reset). When Linux reconfigures the pin to GPIO the short time
LCD_D20 is muxed as LCD_D20 instead of GPIO_1_20 is enough to confuse
the connected IC.

The same problem is present for the pin's drive strength setting which is
reset to low drive strength before using the right value.

So instead of relying on the hardware to modify the register setting
using two writes implement the bit toggling using read-modify-write.

Fixes: 17723111e64f ("pinctrl: add pinctrl-mxs support")
Signed-off-by: Uwe Kleine-König 
Acked-by: Shawn Guo 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: meson: meson8b: fix the NAND DQS pins

2017-07-31T17:37:53+00:00

[ Upstream commit 97ba26b8a9343008504d4e3a87d212bc07b05212 ]

The nand_groups table uses different names for the NAND DQS pins than
the GROUP() definition in meson8b_cbus_groups (nand_dqs_0 vs nand_dqs0).
This prevents using the NAND DQS pins in the devicetree.

Fix this by ensuring that the GROUP() definition and the
meson8b_cbus_groups use the same name for these pins.

Fixes: 0fefcb6876d0 ("pinctrl: Add support for Meson8b")
Signed-off-by: Martin Blumenstingl 
Acked-by: Kevin Hilman 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: qcom: Don't clear status bit on irq_unmask

2017-05-17T19:07:43+00:00

[ Upstream commit a6566710adaa4a7dd5e0d99820ff9c9c30ee5951 ]

Clearing the status bit on irq_unmask will discard any pending interrupt
that did arrive after the irq_ack, i.e. while the IRQ handler function
was executing.

Fixes: f365be092572 ("pinctrl: Add Qualcomm TLMM driver")
Cc: stable@vger.kernel.org
Cc: Stephen Boyd 
Reported-by: Timur Tabi 
Signed-off-by: Bjorn Andersson 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl/amd: Remove the default de-bounce time

2016-08-31T23:21:09+00:00

[ Upstream commit 8cf4345575a416e6856a6856ac6eaa31ad883126 ]

In the function amd_gpio_irq_enable() and
amd_gpio_direction_input(), remove the code which is setting
the default de-bounce time to 2.75ms.

The driver code shall use the same settings as specified in
BIOS. Any default assignment impacts TouchPad behaviour when
the LevelTrig is set to EDGE FALLING.

Cc: stable@vger.kernel.org
Reviewed-by:  Ken Xue 
Signed-off-by: Nitesh Kumar Agrawal 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: cherryview: prevent concurrent access to GPIO controllers

2016-08-16T12:25:04+00:00

[ Upstream commit 0bd50d719b004110e791800450ad204399100a86 ]

Due to a silicon issue on the Atom X5-Z8000 "Cherry Trail" processor
series, a common lock must be used to prevent concurrent accesses
across the 4 GPIO controllers managed by this driver.

See Intel Atom Z8000 Processor Series Specification Update
(Rev. 005), errata #CHT34, for further information.

Cc: stable 
Signed-off-by: Dan O'Donovan 
Acked-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: cherryview: Use raw_spinlock for locking

2016-08-16T12:25:04+00:00

[ Upstream commit 109fdf1572be86aaf681e69b30dc5ada90ce6f35 ]

When running -rt kernel and an interrupt happens on a GPIO line controlled by
Intel Cherryview/Braswell pinctrl driver we get:

 BUG: sleeping function called from invalid context at kernel/locking/rtmutex.c:917
 in_atomic(): 1, irqs_disabled(): 1, pid: 0, name: swapper/0
 Preemption disabled at:[] cpu_startup_entry+0x17f/0x480

 CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.1.5-rt5 #16
  ...
 Call Trace:
    [] dump_stack+0x4a/0x61
  [] ___might_sleep+0xe7/0x170
  [] rt_spin_lock+0x1f/0x50
  [] chv_gpio_irq_ack+0x3d/0xa0
  [] handle_edge_irq+0x75/0x180
  [] generic_handle_irq+0x27/0x40
  [] chv_gpio_irq_handler+0x7e/0x110
  [] handle_irq+0xaa/0x190
  ...

This is because desc->lock is raw_spinlock and is held when chv_gpio_irq_ack()
is called by the genirq core. chv_gpio_irq_ack() in turn takes pctrl->lock
which in -rt is an rt-mutex causing might_sleep() rightfully to complain about
sleeping function called from invalid context.

In order to keep -rt happy but at the same time make sure that register
accesses get serialized, convert the driver to use raw_spinlock instead.

Suggested-by: Linus Walleij 
Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin

pinctrl: cherryview: Serialize all register access

2016-08-16T12:25:03+00:00

[ Upstream commit 4585b000ace6438d0b142746baab658056b223d9 ]

There is a hardware issue in Intel Braswell/Cherryview where concurrent
GPIO register access might results reads of 0xffffffff and writes might get
dropped.

Prevent this from happening by taking the serializing lock for all places
where it is possible that more than one thread might be accessing the
hardware concurrently.

Signed-off-by: Mika Westerberg 
Signed-off-by: Linus Walleij 
Signed-off-by: Sasha Levin