linux-stable.git/drivers/pinctrl, branch v3.16.67

pinctrl: sh-pfc: sh7734: Fix shifted values in IPSR10

2019-04-04T15:13:57+00:00

commit 054f2400f706327f96770219c3065b5131f8f154 upstream.

Some values in the Peripheral Function Select Register 10 descriptor are
shifted by one position, which may cause a peripheral function to be
programmed incorrectly.

Fixing this makes all HSCIF0 pins use Function 4 (value 3), like was
already the case for the HSCK0 pin in field IP10[5:3].

Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: sh7734: Remove bogus IPSR10 value

2019-04-04T15:13:56+00:00

commit 4d374bacd7c9665179f9752a52d5d602c45d8190 upstream.

The IP10[5:3] field in Peripheral Function Select Register 10 has a
width of 3 bits, i.e. it allows programming one out of 8 different
configurations.
However, 9 values are provided instead of 8, overflowing into the
subsequent field in the register, and thus breaking the configuration of
the latter.

Fix this by dropping a bogus zero value.

Fixes: ac1ebc2190f575fc ("sh-pfc: Add sh7734 pinmux support")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: sh7269: Add missing PCIOR0 field

2019-04-04T15:13:56+00:00

commit 9540cbdfcd861caf67a6f0e4bb7f46d41c4aad86 upstream.

The Port C I/O Register 0 contains 7 reserved bits, but the descriptor
contains only dummy configuration values for 6 reserved bits, thus
breaking the configuration of all subsequent fields in the register.

Fix this by adding the two missing configuration values.

Fixes: f5e811f2a43117b2 ("sh-pfc: Add sh7269 pinmux support")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: sh7264: Fix PFCR3 and PFCR0 register configuration

2019-04-04T15:13:55+00:00

commit 1b99d0c80bbe1810572c2cb77b90f67886adfa8d upstream.

The Port F Control Register 3 (PFCR3) contains only a single field.
However, counting from left to right, it is the fourth field, not the
first field.
Insert the missing dummy configuration values (3 fields of 16 values) to
fix this.

The descriptor for the Port F Control Register 0 (PFCR0) lacks the
description for the 4th field (PF0 Mode, PF0MD[2:0]).
Add the missing configuration values to fix this.

Fixes: a8d42fc4217b1ea1 ("sh-pfc: Add sh7264 pinmux support")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: sh7734: Add missing IPSR11 field

2019-04-04T15:13:55+00:00

commit 94482af7055e1ffa211c1135256b85590ebcac99 upstream.

The Peripheral Function Select Register 11 contains 3 reserved bits and
15 variable-width fields, but the variable field descriptor does not
contain the 3-bit field IP11[25:23].

Fixes: 856cb4bb337ee504 ("sh: Add support pinmux for SH7734")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: sh73a0: Add missing TO pin to tpu4_to3 group

2019-04-04T15:13:55+00:00

commit 124cde98f856b6206b804acbdec3b7c80f8c3427 upstream.

The tpu4_to3_mux[] array contains the TPU4TO3 pin mark, but the
tpu4_to3_pins[] array lacks the corresponding pin number.

Add the missing pin number, for non-GPIO pin F26.

Fixes: 5da4eb049de803c7 ("sh-pfc: sh73a0: Add TPU pin groups and functions")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: r8a7791: Remove bogus marks from vin1_b_data18 group

2019-04-04T15:13:54+00:00

commit 0d6256cb880166a4111bebce35790019e56b6e1b upstream.

The vin1_b_data18_mux[] arrays contains pin marks for the 2 LSB bits of
the color components.  The vin1_b_data18_pins[] array rightfully does
not include the corresponding pin numbers, as RGB18 is subset of RGB24,
containing only the 6 MSB bits of each component.

Fixes: 8e32c9671f84acd8 ("pinctrl: sh-pfc: r8a7791: Add VIN pins")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: r8a7791: Remove bogus ctrl marks from qspi_data4_b group

2019-04-04T15:13:54+00:00

commit 884fa25fb6e5e63ab970d612a628313bb68f37cc upstream.

The qspi_data4_b_mux[] array contains pin marks for the clock and chip
select pins.  The qspi_data4_b_pins[] array rightfully does not contain
the corresponding pin numbers, as the control pins are provided by a
separate group (qspi_ctrl_b).

Fixes: 2d0c386f135e4186 ("pinctrl: sh-pfc: r8a7791: Add QSPI pin groups")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: r8a7740: Add missing LCD0 marks to lcd0_data24_1 group

2019-04-04T15:13:54+00:00

commit 96bb2a6ab4eca10e5b6490b3f0738e9f7ec22c2b upstream.

The lcd0_data24_1_pins[] array contains the LCD0 D1[2-5] pin numbers,
but the lcd0_data24_1_mux[] array lacks the corresponding pin marks.

Fixes: 06c7dd866da70f6c ("sh-pfc: r8a7740: Add LCDC0 and LCDC1 pin groups and functions")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings

pinctrl: sh-pfc: r8a7740: Add missing REF125CK pin to gether_gmii group

2019-04-04T15:13:53+00:00

commit 1ebc589a7786f17f97b9e87b44e0fb4d0290d8f8 upstream.

The gether_gmii_mux[] array contains the REF125CK pin mark, but the
gether_gmii_pins[] array lacks the corresponding pin number.

Fixes: bae11d30d0cafdc5 ("sh-pfc: r8a7740: Add GETHER pin groups and functions")
Signed-off-by: Geert Uytterhoeven 
Reviewed-by: Simon Horman 
Signed-off-by: Ben Hutchings